Processor Programming (Continued)
There are five types of test operations that can be exe-
cuted:
times. Once the fill buffer holds a complete cache line of
data (16 bytes), a cache write operation transfers the data
from the fill buffer to the cache.
•
•
•
•
•
Flush buffer read
Fill buffer write
Cache write
Cache read
Cache flush
To read the contents of a cache line, a cache read opera-
tion transfers the data in the selected cache line to the
flush buffer. Once the flush buffer is loaded, access the
contents of the flush buffer with four flush buffer read
operations.
These operations are described in detail in Table 3-18. To
fill a cache line with data, the fill buffer must be written four
Table 3-18. Cache Test Operations
Test Operation
Code Sequence
MOV TR5, 0h
Action Taken
Flush Buffer Read
Set DWORD = 0, control = 00 = flush buffer read.
Flush buffer (31:0) --> dest.
MOV dest,TR3
MOV TR5, 4h
Set DWORD = 1, control = 00 = flush buffer read.
Flush buffer (63:32) --> dest.
MOV dest,TR3
MOV TR5, 8h
Set DWORD = 2, control = 00 = flush buffer read.
Flush buffer (95:64) --> dest.
MOV dest,TR3
MOV TR5, Ch
Set DWORD = 3, control = 00 = flush buffer read.
Flush buffer (127:96) --> dest.
MOV dest,TR3
Fill Buffer Write
MOV TR5, 0h
Set DWORD = 0, control = 00 = fill buffer write.
Cache_data --> fill buffer (31:0).
MOV TR3, cache_data
MOV TR5, 4h
Set DWORD = 1, control = 00 = fill buffer write.
Cache_data --> fill buffer (63:32).
MOV TR3, cache_data
MOV TR5, 8h
Set DWORD = 2, control = 00 = fill buffer write.
Cache_data --> fill buffer (95:64).
MOV TR3, cache_data
MOV TR5, Ch
Set DWORD = 3, control = 00 = fill buffer write.
Cache_data --> fill buffer (127:96).
MOV TR3, cache_data
MOV TR4, cache_tag
MOV TR5, line+set+control=01
MOV TR5, line+set+control=10
MOV dest, TR4
Cache Write
Cache Read
Cache Flush
Cache_tag --> tag address, valid and dirty bits.
Fill buffer (127:0) --> cache line (127:0).
Cache line (127:0) --> flush buffer (127:0).
Cache line tag address, valid/LRU/dirty bits --> dest.
Control = 11 = cache flush, all cache valid bits = 0.
MOV TR5, 3h
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