Power Management (Continued)
Table 5-3. Power Management Programmable Address Region Registers
Bit
Name
Description
Index FFFFFF6Ch
PM_BASE Register (R/W)
Reserved: Set to 0.
Default Value = 0000000h
31:28
27:2
RSVD
BASE_ADDR
Base Address: This is the word-aligned base address for the programmable memory range com-
pare. The actual address range is determined with this field and the PM_MASK register value.
1:0
RSVD
Reserved: Set to 0.
Index FFFFFF7Ch
PM_MASK Register (R/W)
Reserved: Set to 0.
Default Value = 0000000h
31:28
27:2
RSVD
ADR_MASK
Address Mask: This field is the address mask for the BASE_ADDR field in the PM_BASE register.
If a bit in the ADR_MASK field is cleared the corresponding bit in the BASE_ADDR field must match
the processor address. If a bit in the mask field is set high, the corresponding bit in the BASE_ADDR
field always compares. If the processor cycle type matches the values of the WE and RE bits, and all
bits in the BASE_ADDR field match the processor address based on the ADR_MASK field, bit 1 will
be set high in the serial transmission packet.
1
0
WE
RE
Write Enable: Compare memory write cycles with BASE_ADDR and ADR_MASK:
0 = Disable; 1 = Enable.
Read Enable: Compare memory read cycles with BASE_ADDR and ADR_MASK:
0 = Disable; 1 = Enable
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