Architecture Overview (Continued)
.
Pixel Data
18
Pixel Port
(Control & Data)
13
16
Address Control
DRAM Data
24
4
DRAM-A
256Kx16 Bit
Geode™
CS9210
Graphics
Companion
Geode™
CS5530
Geode™
GXLV
Processor
13
16
I/O
Address Control
DRAM Data
Serial
Configuration
DRAM-B
256Kx16 Bit
Companion
8
Video Data
Panel Control
Panel Data
6
DSTN
LCD
24
Figure 1-3. Geode™ CS9210 Interface System Diagram
SYSCLK
SERIALP
IRQ13
GX_CLK
PSERIAL
IRQ13
SMI#
SMI#
PCLK
PCLK
DCLK
DCLK
CRT_HSYNC
CRT_VSYNC
HSYNC
VSYNC
Exclusive
Interconnect
(Note)
PIXEL[17:0]
PIXEL[23:0]
Signals
Not needed if
CRT only (no TFT)
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_VAL
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_VAL
(Do not connect to
any other device)
VID_CLK
VID_CLK
VID_DATA[7:0]
VID_RDY
RESET
VID_DATA[7:0]
VID_RDY
CPU_RST
INTR
INTR
Geode™ GXLV
Processor
Geode™ CS5530
I/O Companion
SUSP#
SUSPA#
AD[31:0]
C/BE[3:0]#
PAR
SUSP#
SUSPA#
AD[31:0]
C/BE[3:0]#
PAR
Nonexclusive
Interconnect
Signals
(May also connect
to other circuitry)
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ0#
GNT0#
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ#
GNT#
Note: Refer to Figure 1-5 for interconnection of the pixel lines.
Figure 1-4. Geode™ GXLV/CS5530 Signal Connections
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