Virtual Subsystem Architecture (Continued)
5.2.5 Virtual VGA Register Descriptions
This section describes the registers contained in the
graphics pipeline used for VGA emulation. The graphics
ters” on page 94 for instructions on accessing these regis-
ters.
The registers are summarized in Table 5-4, followed by
detailed bit formats in Table 5-5 on page 173.
pipeline
maps
200h
locations
starting
at
GX_BASE+8100h. Refer to Section 4.1.2 “Control Regis-
Table 5-4. Virtual VGA Register Summary
GX_BASE+
Memory Offset
Type
Function
Default Value
8210h-8213h
8214h-8217h
8140h-8143h
8144h-8147h
R/W
GP_VGA_BASE VGA
xxxxxxxxh
Graphics Pipeline VGA Memory Base Address Register — Specifies the offset
of the VGA memory, starting from the base of graphics memory.
R/W
R/W
R/W
GP_VGA_LATCH
xxxxxxxxh
xxxxxxxxh
00000000h
Graphics Pipeline VGA Display Latch Register — Provides a memory mapped
way to read or write the VGA display latch.
GP_VGA_WRITE
Graphics Pipeline VGA Write Patch Control Register — Controls the VGA mem-
ory write path in the graphics pipeline.
GP_VGA_READ
Graphics Pipeline VGA Read Patch Control Register — Controls the VGA mem-
ory read path in the graphics pipeline.
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