Integrated Functions (Continued)
4.6.7 PCI Configuration Space Registers
cant bits of the offset are used, and the two least signifi-
cant bits must be 00b.
To access the internal PCI configuration registers of the
GXm processor, the Configuration Address Register
(CONFIG_ADDRESS) must be written as a DWORD
using the format shown in Table 4-38. Any other size will
be interpreted as an I/O write to Port 0CF8h. Also, when
entering the Configuration Index, only the six most signifi-
Table 4-39 summarizes the registers located within the
Configuration Space. The tables that follow, give detailed
register/bit formats.
Table 4-38. Format for Accessing the Internal PCI Configuration Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Configuration Index
0
0
Table 4-39. PCI Configuration Space Register Summary
Index
Type
Name
Default Value
00h-01h
02h-03h
04h-05h
06h-07h
08h
RO
RO
R/W
R/W
RO
RO
RO
R/W
--
Vendor Identification
Device Identification
PCI Command
1078h
0001h
0007h
0280h
00h
Device Status
Revision Identification
Class Code
09h-0Bh
0Ch
060000h
00h
Cache Line Size
Latency Timer
0Dh
0Dh
0Eh-3Fh
40h
Reserved
00h
R/W
R/W
--
PCI Control Function 1
PCI Control Function 2
Reserved
00h
41h
96h
42h
00h
43h
R/W
R/W
--
PCI Arbitration Control 1
PCI Arbitration Control 2
Reserved
80h
44h
00h
45h-FFh
00h
Revision 3.1
157
www.national.com
NSC [ National Semiconductor ]
