Integrated Functions (Continued)
Table 4-30. Display Controller Configuration and Status Registers (Continued)
Bit
Name
Description
GX_BASE+8308h-830Bh
DC_TIMING_CFG Register (R/W)
Default Value = xxx00000h
31
30
VINT
(RO)
Vertical Interrupt (Read Only): Is a vertical interrupt pending? 0 = No; 1 = Yes.
This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3C2h bit
7.
VNA
(RO)
Vertical Not Active (Read Only): Is the active part of a vertical scan is in progress (i.e. retrace, blanking,
or border)? 0 = Yes; 1 = No.
This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3BA/3DA
bit 3.
29
28
DNA
(RO)
Display Not Active (Read Only): Is the active part of a line is being displayed (i.e. retrace, blanking, or
border)? 0 = Yes; 1 = No.
This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3BA/3DA
bit 0.
SENS
(RO)
Monitor Sense (Read Only): This bit returns the result of the voltage comparator test of the RGB lines
from the external RAMDAC. The value will be a low level if one or more of the comparators exceed the 340
mV level indicating an unloaded line.
This bit can be tested repeatedly to determine the loading on the red, green, and blue lines by loading the
palette with various values. The BIOS can then determine whether a color, monochrome, or no monitor is
attached. If no RAMDAC is attached, the BIOS should assume that a color panel is attached and operate
in color mode. For VGA emulation, read operations to port 3C2 bit 4 are redirected here.
27
DDCI
(RO)
DDC Input (Read Only): This bit returns the value from the DDCIN pin that should reflect the value from
pin 12 of the VGA connector. It is used to provide support for the VESA Display Data Channel standard
level DDC1.
26:20
19:17
RSVD
Reserved: Set to 0.
PWR_SEQ
DELAY
Power Sequence Delay: This 3-bit field sets the delay between edges for the power sequencing control
logic. The actual delay is this value multiplied by one frame period (typically 16ms).
Note that a value of zero will result in a delay of only one DOTCLK period.
16
BKRT
Blink Rate:
0 = Cursor blinks on every 16 frames for a duration of 8 frames (approximately 4 times per second) and
VGA text characters will blink on every 32 frames for a duration of 16 frames (approximately 2 times per
second).
1 = Cursor blinks on every 32 frames for a duration of 16 frames (approximately 2 times per second) and
VGA text characters blink on every 64 frames for a duration of 32 frames (approximately 1 time per sec-
ond).
15
14
PXDB
INTL
Pixel Double: Allow pixel doubling to stretch the displayed image in the horizontal dimension:
0 = Disable; 1 = Enable.
If bit 15 is enabled, timing parameters should be programmed as if no pixel doubling is used, however, the
frame buffer should be loaded with half the normal pixels per line. Also, the FB_LINE_SIZE parameter in
DC_BUF_SIZE should be set for the number of bytes to be transferred for the line rather than the number
displayed.
Interlace Scan: Allow interlaced scan mode:
0 = Disable (non-interlaced scanning is supported)
1 = Enable (If a flat panel is attached, it should be powered down before setting this bit.)
VGA Planar Mode: This bit must be set high for all VGA planar display modes.
13
12
PLNR
FCEN
Flat Panel Center: Allows the border and active portions of a scan line to be qualified as “active” to a flat
panel display via the ENADISP signal. This allows the use of a large border region for centering the flat
panel display. 0 = Disable; 1 = Enable.
When disabled, only the normal active portion of the scan line will be qualified as active.
Flat Panel Vertical Sync Polarity:
11
10
FVSP
FHSP
0 = Causes TFT vertical sync signal to be normally low, generating a high pulse during sync interval.
1 = Causes TFT vertical sync signal to be normally high, generating a low pulse during sync interval.
Flat Panel Horizontal Sync Polarity:
0 = Causes TFT horizontal sync signal to be normally low, generating a high pulse during sync interval.
1 = Causes TFT horizontal sync signal to be normally high, generating a low pulse during sync interval.
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