Signal Definitions (Continued)
Index Corner
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
B
A
VSS VSS AD27 AD24 AD21 AD16 VCC2 FRAM#DEVS# VCC3 PERR# AD15 VSS AD11 CBE0# AD6 VCC2 AD4 AD2 VCC3 AD0 AD1 TEST2 MD2 VSS VSS
VSS VSS AD28 AD25 AD22 AD18 VCC2 CBE2# TRDY# VCC3 LOCK# PAR AD14 AD12 AD9 AD7 VCC2 INTR AD3 VCC3 TEST1 TEST3 MD1 MD33 VSS VSS
B
C
C
AD29 AD31 AD30 AD26 AD23 AD19 VCC2 AD17 IRDY# VCC3 STOP#SERR# CBE1# AD13 AD10 AD8 VCC2 AD5 SMI# VCC3 TEST0 IRQ13 MD32 MD34 MD3 MD35
D
D
GNT0# TDI REQ2# VSS CBE3# VSS VCC2 VSS VSS VCC3 VSS VSS VSS VSS VSS VSS VCC2 VSS VSS VCC3 VSS MD0
VSS MD4 MD36 TDN
MD6 TDP MD5 MD37
VSS MD38 MD7 MD39
VCC3 VCC3 VCC3 VCC3
E
E
GNT2#SUSPA#REQ0# AD20
TD0 GNT1# TEST VSS
VCC3 VCC3 VCC3 VCC3
F
F
G
G
H
H
TMS SUSP#REQ1# VSS
FPVSY TCLK RESET VSS
VCC2 VCC2 VCC2 VCC2
CKM1 FPHSYSERLP VSS
VSS MD8 MD40 MD9
VSS MD41 MD10 MD42
VCC2 VCC2 VCC2 VCC2
VSS MD11 MD43 MD12
J
J
K
K
L
L
M
N
M
N
CKM2 VIDVAL CKM0 VSS
VSS MD44 MD13 MD45
VSS MD14 MD46 MD15
Geode™ GXm
VSS PIX1 PIX0 VSS
P
P
Processor
VIDCLK PIX3 PIX2 VSS
VSS MD47 CASA#SYSCLK
VSS WEB# WEA# CASB#
R
R
PIX4 PIX5 PIX6 VSS
T
T
352 BGA - Top View
PIX7 PIX8 PIX9 VSS
VSS DQM0 DQM4 DQM1
VCC3 VCC3 VCC3 VCC3
VSS DQM5 CS2# CS0#
VSS RASA#RASB# MA0
VCC2 VCC2 VCC2 VCC2
VSS MA1 MA2 MA3
MA4 MA5 MA6 MA7
U
U
VCC3 VCC3 VCC3 VCC3
PIX10 PIX11 PIX12 VSS
PIX13 CRTHS PIX14 VSS
VCC2 VCC2 VCC2 VCC2
PIX15 PIX16 CRTVS VSS
DCLK PIX17 VDAT6 VDAT7
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
PCLK FLT# VDAT4 VSS VOLDET VSS VCC2 VSS VSS VCC3 VSS VSS VSS VSS VSS VSS VCC2 VSS VSS VCC3 VSS DQM6 VSS MA8 MA9 MA10
VRDY VDAT5 VDAT3 VDAT0 EDISP MD63 VCC2 MD62 MD29 VCC3 MD59 MD26 MD56 MD55 MD22 CKEB VCC2 MD51 MD18 VCC3 MD48 DQM3 CS1# MA11 BA0
BA1
VSS VSS VDAT2 SCLK3 SCLK1RWCLK VCC2 SCKIN MD61 VCC3 MD28 MD58 MD25 MD24 MD54 MD21 VCC2 MD20 MD50 VCC3 MD17 DQM7 CS3# MA12 VSS VSS
VSS VSS VDAT1 SCLK0 SCLK2 MD31 VCC2SCKOUTMD30 VCC3 MD60 MD27 MD57 VSS MD23 MD53 VCC2 MD52 MD19 VCC3 MD49 MD16 DQM2 CKEA VSS VSS
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Note: Signal names have been abbreviated in this figure due to space constraints.
= GND terminal
= PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-2. 352 BGA Pin Assignment Diagram
For order information refer to Section A.1 “Order Information” on page 236.
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