Integrated Functions (Continued)
Table 4-16. Memory Controller Registers (Continued)
Bit
Name
Description
GX_BASE+840Ch-840Fh
MC_SYNC_TIM1 (R/W)
Default Value = 2A733225h
31
RSVD
Reserved: Set to 0.
30:28
LTMODE
CAS Latency (LTMODE): CAS latency is the delay, in clock cycles, between the registration of a read
command and the availability of the first piece of output data (BIOS interrogates EEPROM across the
2
I C interface to determine this value):
000 = Reserved
001 = 1 CLK
010 = 2 CLK
011 = 3 CLK
100 = 4 CLK
101 = 5 CLK
110 = 6 CLK
111 = 7 CLK
This field will not take effect until SDRAMPRG (bit 0 of MC_MEM_CNTRL1) transitions from 0 to 1.
ERRATA: CAS Latency of 1 CLK is not currently supported.
27:24
23:20
RC
REF to REF/ACT Command Period (tRC): Minimum number of SDRAM clock between REF and
REF/ACT commands:
0000 = Reserved 0100 = 5 CLK
1000 = 9 CLK
1001 = 10 CLK
1010 = 11 CLK
1011 = 12 CLK
1100 = 13 CLK
1101 = 14 CLK
1110 = 15 CLK
1111 = 16 CLK
0001 = 2 CLK
0010 = 3 CLK
0011 = 4 CLK
0101 = 6 CLK
0110 = 7 CLK
0111 = 8 CLK
RAS
ACT to PRE Command Period (tRAS): Minimum number of SDRAM clocks between ACT and PRE
commands:
0000 = Reserved 0100 = 5 CLK
1000 = 9 CLK
1001 = 10 CLK
1010 = 11 CLK
1011 = 12 CLK
1100 = 13 CLK
1101 = 14 CLK
1110 = 15 CLK
1111 = 16 CLK
0001 = 2 CLK
0010 = 3 CLK
0011 = 4 CLK
0101 = 6 CLK
0110 = 7 CLK
0111 = 8 CLK
19
RSVD
RP
Reserved: Set to 0.
18:16
PRE to ACT Command Period (tRP): Minimum number of SDRAM clocks between PRE and ACT
commands:
000 = Reserved
001 = 1 CLK
010 = 2 CLK
011 = 3 CLK
100 = 4 CLK
101 = 5 CLK
110 = 6 CLK
111 = 7 CLK
15
RSVD
RCD
Reserved: Set to 0.
14:12
Delay Time ACT to READ/WRT Command (tRCD): Minimum number of SDRAM clock between ACT
and READ/WRT commands:
000 = Reserved
001 = 1 CLK
010 = 2 CLK
011 = 3 CLK
100 = 4 CLK
101 = 5 CLK
110 = 6 CLK
111 = 7 CLK
11
RSVD
RRD
Reserved: Set to 0.
10:8
ACT(0) to ACT(1) Command Period (tRRD): Minimum number of SDRAM clocks between ACT and
ACT command to two different component banks within the same module bank. The memory control-
ler does not perform back-to-back Activate commands to two different component banks without a
READ or WIRTE command between them. Hence, this field should be set to 001.
7
RSVD
DPL
Reserved: Set to 0.
6:4
Data-in to PRE command period (tDPL): Minimum number of SDRAM clocks from the time the last
write datum is sampled till the bank is precharged:
000 = Reserved
001 = 1 CLK
010 = 2 CLK
011 = 3 CLK
100 = 4 CLK
101 = 5 CLK
110 = 6 CLK
111 = 7 CLK
3:0
RSVD
Reserved: Set to 0 or leave unchanged.
MC_GBASE_ADD (R/W)
GX_BASE+8414h-8417h
Default Value = 00000000h
31:18
17
RSVD
TE
Reserved: Set to 0.
Test Enable TEST[3:0]:
0 = TEST[3:0] are driven low
1 = TEST[3:0] pins are used to output test information
16
TECTL
Test Enable Shared Control Pins:
0 = RASB#, CASB#, CKEB, WEB# are driven low
1 = RASB#, CASB#, CKEB, WEB# are used to output test information
Select: This field is used for debug purposes only.
Reserved: Set to 0.
15:12
11
SEL
RSVD
Revision 3.1
111
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