Processor Programming (Continued)
that no internal SMIs are generated in SMM, so the pro-
cessor ignores such events. If the internal and external
SMI signals are received simultaneously, then the internal
SMI is given priority to avoid losing the event.
set high. The microcode clears SMI_NEST, sets
Nested SMI Status high and saves the previous
value of Nested SMI Status (1) in the SMI header.
E. The second-level SMI handler saves the header and
sets SMI_NEST to re-enable SMI interrupts within
SMM. Another level of nesting could occur during
this period.
The state diagram of the SMI_NEST and Nested SMI Sta-
tus bits are shown in Figure 3-11 with each state
explained next.
A. When the processor is outside of SMM, Nested SMI
Status is always clear and SMI_NEST is set high.
F. The second-level SMI handler clears SMI_NEST to
disable SMI interrupts, then restores its SMI header.
B. The first-level SMI interrupt is received by the
processor. The microcode clears SMI_NEST, sets
Nested SMI Status high and saves the previous
value of Nested SMI Status (0) in the SMI header.
G. The second-level SMI handler executes an RSM.
The microcode sets SMI_NEST, and restores the
Nested SMI Status (1) based on the SMI header.
H. The first-level SMI handler clears SMI_NEST to
disable SMI interrupts, then restores its SMI header.
C. The first-level SMI handler saves the header and
sets SMI_NEST high to re-enable SMI interrupts
from SMM.
I. The first-level SMI handler executes an RSM. The
microcode sets SMI_NEST high and restores the
Nested SMI Status (0) based on the SMI header.
D. A second-level (nested) SMI interrupt is received by
the processor. This SMI is taken even though the
processor is in SMM because the SMI_NEST bit is
When the processor is outside of SMM, Nested SMI Sta-
tus is always clear and SMI_NEST is set high.
SMI_NEST
Nested SMI Status
A
B
C
D
E
F
G
H
I
Figure 3-11. SMI Nesting State Machine
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