Processor Programming (Continued)
Table 3-7. CR4-CR0 Bit Definitions (Continued)
Bit
Name Description
CR2 Register
Control Register 2 (R/W)
31:0
PFLA
Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the
address that caused the page fault.
CR1 Register
Control Register 1 (R/W)
31:0
RSVD Reserved
CR0 Register
Control Register 0 (R/W)
31
30
PG
Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing the
state of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change
take effect.
CD
Cache Disable: If CD = 1, no further cache line fills occur. However, data already present in the cache continues
to be used if the requested address hits in the cache. Writes continue to update the cache and cache invalida-
tions due to inquiry cycles occur normally. The cache must also be invalidated with a WBINVD instruction to com-
pletely disable any cache activity.
29
NW
Not Write-Through: If NW = 1, the on-chip cache operates in write-back mode. In write-back mode, writes are
issued to the external bus only for a cache miss, a line replacement of a modified line, execution of a locked
instruction, or a line eviction as the result of a flush cycle. If NW = 0, the on-chip cache operates in write-through
mode. In write-through mode, all writes (including cache hits) are issued to the external bus. This bit cannot be
changed if LOCK_NW = 1 in CCR2.
28:19
18
RSVD Reserved
AM Alignment Check Mask: If AM = 1, the AC bit in the EFLAGS register is unmasked and allowed to enable align-
ment check faults. Setting AM = 0 prevents AC faults from occurring.
RSVD Reserved
WP Write Protect: Protects read-only pages from supervisor write access. WP = 0 allows a read-only page to be
written from privilege level 0-2. WP = 1 forces a fault on a write to a read-only page from any privilege level.
RSVD Reserved
NE Numerics Exception: NE = 1 to allow FPU exceptions to be handled by interrupt 16. NE = 0 if FPU exceptions
are to be handled by external interrupts.
RSVD Reserved: Do not attempt to modify, always 1.
17
16
15:6
5
4
3
TS
Task Switched: Set whenever a task switch operation is performed. Execution of a floating point instruction with
TS = 1 causes a DNA fault. If MP = 1 and TS = 1, a WAIT instruction also causes a DNA fault.
2
1
EM
MP
Emulate Processor Extension: If EM = 1, all floating point instructions cause a DNA fault 7.
Monitor Processor Extension: If MP = 1 and TS = 1, a WAIT instruction causes Device Not Available (DNA)
fault 7. The TS bit is set to 1 on task switches by the CPU. Floating point instructions are not affected by the state
of the MP bit. The MP bit should be set to one during normal operations.
0
PE
Protected Mode Enable: Enables the segment based protection mechanism. If PE = 1, protected mode is
enabled. If PE = 0, the CPU operates in real mode and addresses are formed as in an 8086-style CPU. Refer to
Section 3.9 “Protection” on page 91.
Table 3-8. Effects of Various Combinations of EM, TS, and MP Bits
CR0[3:1]
EM
Instruction Type
TS
MP
WAIT
ESC
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Execute
Execute
Execute
Fault 7
Execute
Execute
Fault 7
Fault 7
Fault 7
Fault 7
Fault 7
Fault 7
Execute
Execute
Execute
Fault 7
Revision 1.1
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