Instruction Set (Continued)
8.3 PROCESSOR CORE INSTRUCTION SET
The instruction set for the GXLV processor core is sum-
marized in Table 8-27. The table uses several symbols
and abbreviations that are described next and listed in
Table 8-26.
Table 8-26. Processor Core Instruction Set
Table Legend
Symbol or
Abbreviation
Description
8.3.1 Opcodes
Opcode
Opcodes are given as hex values except when they
appear within brackets as binary values.
#
##
Immediate 8-bit data.
Immediate 16-bit data.
###
+
Full immediate 32-bit data (8, 16, 32 bits).
8-bit signed displacement.
8.3.2 Clock Counts
The clock counts listed in the instruction set summary
table are grouped by operating mode (real and protected)
and whether there is a register/cache hit or a cache miss.
In some cases, more than one clock count is shown in a
column for a given instruction, or a variable is used in the
clock count.
+++
Full signed displacement (16, 32 bits).
Clock Count
/
n
L
|
Register operand/memory operand.
Number of times operation is repeated.
Level of the stack frame.
8.3.3 Flags
Conditional jump taken | Conditional jump not
taken. (e.g. “4|1” = 4 clocks if jump taken, 1
clock if jump not taken).
There are nine flags that are affected by the execution of
instructions. The flag names have been abbreviated and vari-
ous conventions used to indicate what effect the instruc-
tion has on the particular flag.
\
CPL ≤ IOPL \ CPL > IOPL
(where CPL = Current Privilege Level, IOPL =
I/O Privilege Level).
Flags
OF
DF
IF
Overflow Flag.
Direction Flag.
Interrupt Enable Flag.
Trap Flag.
TF
SF
ZF
AF
PF
CF
x
Sign Flag.
Zero Flag.
Auxiliary Flag.
Parity Flag.
Carry Flag.
Flag is modified by the instruction.
Flag is not changed by the instruction.
Flag is reset to “0”.
Flag is set to “1”.
-
0
1
u
Flag is undefined following execution the
instruction.
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