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30134-23 参数 Datasheet PDF下载

30134-23图片预览
型号: 30134-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用: 外围集成电路时钟
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Signal Definitions (Continued)  
2.1 PIN ASSIGNMENTS  
The tables in this section use several common abbrevia-  
tions. Table 2-1 lists the mnemonics and their meanings.  
Table 2-1. Pin Type Definitions  
Mnemonic Definition  
Standard input pin.  
Figure 2-2 shows the pin assignment for the 352 BGA with  
Table 2-2 and Table 2-3 listing the pin assignments sorted  
by pin number and alphabetically by signal name, respec-  
tively.  
I
I/O  
O
Bidirectional pin.  
Totem-pole output.  
OD  
Open-drain output structure that  
allows multiple devices to share the  
pin in a wired-OR configuration.  
Figure 2-3 shows the pin assignment for the 320 SPGA  
with Table 2-4 and Table 2-5 listing the pin assignments  
sorted by pin number and alphabetically by signal name,  
respectively.  
PU  
Pull-up resistor.  
PD  
Pull-down resistor.  
In Section 2.2 “Signal Descriptions” on page 31 a descrip-  
tion of each signal is provided within its associated func-  
tional group.  
s/t/s  
Sustained tri-state an active-low tri-  
state signal owned and driven by  
one and only one agent at a time.  
The agent that drives an s/t/s pin low  
must drive it high for at least one  
clock before letting it float. A new  
agent cannot start driving an s/t/s  
signal any sooner than one clock  
after the previous owner lets it float.  
A pull-up resistor on the mother-  
board is required to sustain the inac-  
tive state until another agent drives  
it.  
VCC (PWR)  
VSS (GND)  
#
Power pin.  
Ground pin.  
The "#" symbol at the end of a signal  
name indicates that the active, or  
asserted state occurs when the sig-  
nal is at a low voltage level. When  
"#" is not present after the signal  
name, the signal is asserted when at  
a high voltage level.  
t/s  
Tri-state signal.  
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