Integrated Functions (Continued)
4.5.7.3 VGA Display Support
attributes in the VGA buffer to an 8-bpp frame buffer
image the hardware uses for display refresh.
The graphics pipeline contains full hardware support for
the VGA front end. The VGA data is stored in a 256 KB
buffer located in graphics memory. The main task for Vir-
tual VGA (see Section 4.6 “Virtual VGA Subsystem” on
page 157) is converting the data in the VGA buffer to an 8-
bpp frame buffer that can be displayed by the display con-
troller.
4.5.8 Display Controller Registers
The Display Controller maps 100h memory locations
starting at GX_BASE+8300h for the display controller reg-
isters. Refer to Section 4.1.2 “Control Registers” on page
99 for instructions on accessing these registers.
The Display Controller Registers are divided into six cate-
gories:
For some modes, the display controller can display the
VGA data directly and the data conversion is not neces-
sary. This includes standard VGA mode 13h and the vari-
ations of that mode used in several games; the display
controller can also directly display VGA planar graphics
modes D, E, F, 10, 11, and 12. Likewise, the hardware can
directly display all of the higher-resolution VESA modes.
Since the frame buffer data is written directly to memory
instead of travelling across an external bus, the GXLV pro-
cessor often outperforms VGA cards for these modes.
•
•
•
•
•
•
Configuration and Status Registers
Memory Organization Registers
Timing Registers
Cursor and Line Compare Registers
Color Registers
Palette and RAM Diagnostic Registers
Table 4-28 summarizes these registers and locations, and
the following subsections give detailed register/bit for-
mats.
The display controller, however, does not directly support
text modes. SoftVGA must convert the characters and
Table 4-28. Display Controller Register Summary
GX_BASE+
Memory Offset
Default
Value
Type
Name/Function
Configuration and Status Registers
8300h-8303h
R/W
DC_UNLOCK
00000000h
Display Controller Unlock: This register is provided to lock the most critical memory-
mapped display controller registers to prevent unwanted modification (write operations).
Read operations are always allowed.
8304h-8307h
8308h-830Bh
R/W
R/W
DC_GENERAL_CFG
00000000h
xx000000h
Display Controller General Configuration: General control bits for the display controller.
DC_TIMING_CFG
Display Controller Timing Configuration: Status and control bits for various display
timing functions.
830Ch-830Fh
R/W
DC_OUTPUT_CFG
xx000000h
Display Controller Output Configuration: Status and control bits for pixel output
formatting functions.
Memory Organization Registers
8310h-8313h
8314h-8317h
8318h-831Bh
R/W
R/W
R/W
DC_FB_ST_OFFSET
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
Display Controller Frame Buffer Start Address: Specifies offset at which the frame buffer
starts.
DC_CB_ST_OFFSET
Display Controller Compression Buffer Start Address: Specifies offset at which the com-
pressed display buffer starts.
DC_CUR_ST_OFFSET
Display Controller Cursor Buffer Start Address: Specifies offset at which the cursor mem-
ory buffer starts.
831Ch-831Fh
8320h-8323h
--
Reserved
00000000h
xxxxxxxxh
R/W
DC_VID_ST_OFFSET
Display Controller Video Start Address: Specifies offset at which the video buffer starts.
DC_LINE_DELTA
8324h-8327h
R/W
xxxxxxxxh
Display Controller Line Delta: Stores line delta for the graphics display buffers.
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