Signal Definitions (Continued)
2.2.2 PCI Interface Signals (Continued)
BGA
SPGA
Signal Name
Pin No. Pin No
Type
Description
Grant Lines
GNT[2:0]#
E1,
F2,
D1
H2,
K4,
F2
O
Grant indicates to the requesting master that it has been granted
access to the bus. Each master has its own GNT# line. GNT#
can be pulled away at any time a higher REQ# is received or if
the master does not begin a cycle within a minimum period of
time (16 SYSCLKs).
2.2.3 Memory Controller Interface Signals
BGA SPGA
Signal Name
Pin No. Pin No.
Type
Description
Note: The memory controller interface supports two types of memory configurations: SDRAM modules on the sys-
tem board and JEDEC DIMM connectors. Refer to Section 4.3 “Memory Controller” on page 103 for detailed
information regarding signal connections.
MD[63:0]
Refer
Refer
I/O
Memory Data Bus
toTable toTable
The data bus lines driven to/from system memory.
2-3
2-5
MA[12:0]
Refer
Refer
O
Memory Address Bus
toTable toTable
The multiplexed row/column address lines driven to the system
memory.
2-3
2-5
Supports 256 Mbit SDRAM.
BA[1:0]
AD26,
AD25
AJ33,
AK36
O
O
Bank Address Bits
These bits are used to select the component bank within the
SDRAM.
CS[3:0]#
AE23,
V25,
AD23,
V26
AK32,
Z34,
AN33,
AA35
Chip Selects
The chip selects are used to select the module bank within the
system memory. Each chip select corresponds to a specific mod-
ule bank.
If CS# is high, the bank(s) do not respond to RAS#, CAS#, WE#
until the bank is selected again.
RASA#,
RASB#
W24,
W25
AB36,
AB34
O
O
O
Row Address Strobe
RAS#, CAS#, WE# and CKE are encoded to support the differ-
ent SDRAM commands. RASA# is used with CS[1:0]#. RASB#
is used with CS[3:2]#.
CASA#,
CASB#
P25,
R26
W37,
X36
Column Address Strobe
RAS#, CAS#, WE# and CKE are encoded to support the differ-
ent SDRAM commands. CASA# is used with CS[1:0]#. CASB#
is used with CS[3:2]#.
WEA#,
WEB#
R25,
R24
W33,
W35
Write Enable
RAS#, CAS#, WE# and CKE are encoded to support the differ-
ent SDRAM commands. WEA# is used with CS[1:0]#. WEB# is
used with CS[3:2]#.
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