Processor Programming (Continued)
Real and Virtual 8086 Modes
Logical Address
Segment Selector
INDEX
15
0
INSTRUCTION OFFSET
Logical
Address
x 16
+
p
Segment
Base
Address
Linear
Address
Physical
Address
p = Paging mechanism for virtual 8086 mode only
Main Memory
Protected Mode
Logical Address
Segment Selector
15
3
2
1
0
INSTRUCTION OFFSET
INDEX
TI RPL
Segment Descriptor
p
÷ 8
+
Segment
Base
Address
Linear
Address
Physical
Address
GDT or LDT Descriptor Table
p = Paging mechanism
Main Memory
Figure 3-6. Selector Mechanisms
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