Electrical Specifications (Continued)
Table 6-14. Clock Signals (Refer to Figures 6-5 and 6-6) (Continued)
SYSCLK = 33 MHz SYSCLK = 30 MHz
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
Units Comments
t12
SDCLK_OUT, SDCLK[3:0] Fall Time
166 MHz / 2.5
180 MHz / 2.5
180 MHz / 3
200 MHz / 3
233 MHz / 3
233 MHz / 3.5
266 MHz / 3.5
266 MHz / 4
0.5
ns
Note 3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
t13
SDCLK_OUT, SDCLK[3:0] Rise Time
166 MHz
180 MHz
180 MHz
200 MHz
233 MHz
233 MHz
266 MHz
266 MHz
0.45
ns
Note 3
0.45
0.45
0.45
0.45
Notes: 1. A SYSCLK of 30 MHz corresponds to a core frequency of 180 MHz. A SYSCLK of 33 MHz corresponds to
core frequencies of 166, 200, 233, and 266 MHz.
2. SDCLK calculations are based on the following officially supported configurations:
166 MHz (5x) / 2.5 = 66.4 MHz SDCLK_OUT
180 MHz (5x) / 2.5 = 72 MHz SDCLK_OUT
180 MHz (6x) / 3 = 60 MHz SDCLK_OUT
200 MHz (6x) / 3 = 66.7 MHz SDCLK_OUT
233 MHz (7x) / 3 = 77.7 MHz SDCLK_OUT
233 MHz (7x) / 3.5 = 66.6 MHz SDCLK_OUT
266 MHz (8x) / 3.5 = 76 MHz SDCLK_OUT
266 MHz (8x) / 4 = 66.5 MHz SDCLK_OUT
3. SDCLK_OUT and SYSCLK rise and fall times are measured between VIH min and VIL max with a 50 pF
load.
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