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30070-53 参数 Datasheet PDF下载

30070-53图片预览
型号: 30070-53
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用: 外围集成电路时钟
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Integrated Functions (Continued)  
4.7.8.3 PCI Arbitration  
REQ#-b on CLK 6. The PCI arbiter can then grant access  
to Agent A, and does so on CLK 7. Note that all buffers  
must flush before a grant is given to a new agent.  
An agent requests the bus by asserting its REQ#. Based  
on the arbitration scheme set in the PCI Arbitration Con-  
trol 2 Register (Index 44h), the GXLV processors PCI  
arbiter will grant the request by asserting GNT#. Figure 4-  
20 illustrates basic arbitration.  
For additional information refer to Chapter 3.4.1, Arbitra-  
tion Signaling Protocol, of the PCI Local Bus Specifica-  
tion, Revision 2.1.  
REQ#-a is asserted at CLK 1. The PCI arbiter grants  
access to Agent A by asserting GNT#-a on CLK 2. Agent  
A must begin a transaction by asserting FRAME# within  
16 clocks, or the GXLVs PCI arbiter will remove GNT#.  
Also, it is possible for Agent A to lose bus ownership  
sooner if another agent with higher priority requests the  
bus. However, in this example, Agent B is of higher priority  
than Agent A. When Agent B requests the bus on CLK 2,  
Agent A is allowed to proceed per Specification. Agent A  
starts its transaction on CLK 3 by asserting FRAME# and  
completes its transaction. Since Agent A requests another  
transaction, REQ#-a remains asserted. When FRAME# is  
asserted on CLK 3, the PCI arbiter determines Agent B  
should go next, asserts GNT#-b and deasserts GNT#-a  
on CLK 4. Agent B requires only a single transaction. It  
completes the transaction, then deasserts FRAME# and  
4.7.8.4 PCI Halt Command  
Halt is a broadcast message from the GXLV processor  
indicating it has executed a HALT instruction. The PCI  
Special Cycle command is used to broadcast the mes-  
sage to all agents on the bus segment. During the  
address phase of the Halt Special cycle, C/BE[3:0]# =  
0001 and AD[31:0] are driven to arbitrary values. During  
the data phase, C/BE[3:0]# = 1100 indicating bytes 1 and  
0 are valid and AD[15:0] = 0001h.  
For additional information, refer to Chapter 3.7.2, Special  
Cycle, and Appendix A, Special Cycle Messages, of the  
PCI Local Bus Specification, Revision 2.1.  
1
2
3
4
5
6
7
8
9
CLK  
REQ#-a  
REQ#-b  
GNT#-a  
GNT#-b  
FRAME#  
AD  
ADDR  
ADDR  
DATA  
DATA  
Agent-A  
Agent-B  
Figure 4-20. Basic Arbitration  
Revision 1.1  
175  
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