Signal Definitions (Continued)
Index Corner
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
A
B
A
VCC3
AD25
VSS
VCC2
AD16
AD18
VCC2
VCC3
CBE2# TRDY#
FRAME#
AD17 IRDY#
DEVSEL#
STOP#
SERR#
VSS
VCC3
VSS
AD11
AD10
AD8
VSS
AD5
VCC3
AD4
AD2
AD0
VCC2
VCC2
VCC2
VSS
TEST0
MD1
VCC3
MD34
MD36
MD37
VSS
VSS
VCC3
NC
B
VSS
AD27
AD29
TDI
CBE3#
AD21
AD22
AD19
AD20
LOCK#
CBE1#
AD13
AD12
AD9
AD7
AD6
AD3
SMI#
AD1
MD0
TEST2
MD33
MD3
MD2
MD35
NC
C
C
VCC3
AD31
AD26
AD28
VSS
AD23
VSS
VCC2
VCC2
VSS
PAR
IRQ13
VSS
D
D
AD30
AD24
PERR#
AD14
INTR
TEST1
TEST3
MD32
E
E
REQ0#
REQ2#
VSS
AD15
CBE0#
VSS
VCC2
MD4
F
F
GNT0#
GNT2#
REQ1#
MD5
G
G
VSS
CKMD2
VSS
VSS
H
H
SUSPA#
TEST
GNT1#
VCC2
MD6
MD38
MD8
J
J
TDO
VSS
VCC2
VCC2
VSS
MD7
VCC2
VCC3
MD43
MD45
VSS
K
K
MD39
MD40
MD10
MD44
MD15
L
L
VCC2
VCC2
VCC2
MD41
VSS
M
M
RESET
VCC3
SUSP#
MD9
N
N
TMS
VSS
VSS
P
P
FPVSYNC
TCLK
MD42
MD12
MD46
MD47
Q
Q
SERIALP
NC
Geode™
MD11
MD14
VSS
R
R
CKMD1 FPHSYNC
CKMD0 VID_VAL PIX0
PIX1 PIX2
S
S
MD13
GXLV
T
T
U
U
Processor
VSS
VCC3
VSS
PIX4
PIX7
VSS
VCC3
V
V
PIX3
NC
VID_CLK
SYSCLK
WEA# WEB#
CASB#
W
X
W
X
PIX6
PIX5
VSS
CASA#
PIX9
PIX10
PIX13
DQM0
320 SPGA - Top View
Y
Y
PIX8
DQM1
VSS
DQM4
Z
Z
NC
CS2#
DQM5
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
VCC3
PIX11
VSS
CS0#
VCC3
PIX12
RASB#
RASA#
VCC2
VCC2
VCC2
VCC2
VSS
VCC2
VCC2
VSS
VCC2
VSS
VCC2
MA1
VSS
CRTHSYNC DCLK
MA2
MA4
MA8
VSS
MA0
MA3
MA6
BA0
NC
PIX14
VSS
PIX15
PIX16
VSS
PIX17
MA5
CRTVSYNC VDAT6
MA10
CS3#
DQM2
PCLK
VCC2
FLT#
VDAT5
VDAT0
VDAT2 SDCLK1
VSS
VCC2
MD31
VSS
MD60
VSS
MD57
MD58
MD26
VSS
VCC3
VSS
MD22
MD23
MD54
MD52
VSS
VSS
VCC2
MD49
MD17
VCC2
VCC2
VCC2
VSS
DQM6
VSS
BA1
MA9
MA7
VCC3
VSS
VRDY
VDAT4
VDAT7 VDAT3
VSS
SDCLK0 SDCLK2 SDCLKIN
VCC2
SDCLK3
MD29
MD61
MD27
MD59
MD56
MD25
MD55
MD24
MD21
MD53
MD20
MD51
MD50
MD18
MD16
MD48
DQM3
DQM7
RWCLK SDCLKOUT
MD19
VCC3
CKEA
CS1#
MA11
VCC3
ENDIS
MD63
MD30
MA12
VSS
VCC2
VDAT1
VSS
VCC2
MD62
VCC3
MD28
CKEB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Note: Signal names have been abbreviated in this figure due to space constraints.
= Denotes GND terminal
= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-3. 320 SPGA Pin Assignment Diagram
For order information, refer to Section A.1 “Order Information” on page 246.
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