Processor Programming (Continued)
Table 3-39. FPU Registers
Bit
Name
Description
FPU Tag Word Register (R/W) (Note)
15:14
13:12
11:10
9:8
TAG7
TAG6
TAG5
TAG4
TAG3
TAG2
TAG1
TAG0
TAG7: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.
TAG6: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.
TAG5: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.
TAG4: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.
TAG3: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.
TAG2: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.
TAG1: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.
TAG0: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.
7:6
5:4
3:2
1:0
FPU Status Register (R/W) (Note)
15
B
C3
S
Copy of ES bit (bit 7 this register)
14
Condition code bit 3
13:11
Top-of-Stack: Register number that points to the current TOS.
Condition code bits [2:0]
10:8
7
C[2:0]
ES
SF
P
Error indicator: Set to 1 if unmasked exception detected.
Stack Full: FPU Status Register: or invalid register operation bit.
Precision error exception bit
6
5
4
U
Underflow error exception bit
3
O
Overflow error exception bit
2
Z
Divide-by-zero exception bit
1
D
Denormalized-operand error exception bit
Invalid operation exception bit
0
I
FPU Mode Control Register (R/W) (Note)
15:12
11:10
RSVD
RC
Reserved: Set to 0.
Rounding Control Bits:
00 = Round to nearest or even
01 = Round towards minus infinity
10 = Round towards plus infinity
11 = Truncate
9:8
PC
Precision Control Bits:
00 = 24-bit mantissa
01 = Reserved
10 = 53-bit mantissa
11 = 64-bit mantissa
7:6
5
RSVD
Reserved: Set to 0.
P
U
O
Z
D
I
Precision error exception bit
FPU Mode Control Register
Overflow error exception bit
Divide-by-zero exception bit
Denormalized-operand error exception bit
Invalid-operation exception bit
4
3
2
1
0
Note: R/W only through the environment at store and restore commands.
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