Processor Programming (Continued)
Bits [21:12] of the 32-bit linear address, referred to as the
Page Table Index (PTI), locate a 32-bit entry in the sec-
ond-level page table. This Page Table Entry (PTE) con-
tains the base address of the desired page frame. The
second-level page table addresses up to 1K individual
page frames. A second-level page table is 4 KB in size
and is itself a page. Bits [11:0] of the 32-bit linear address,
the Page Frame Offset (PFO), locate the desired physical
data within the page frame.
The present bits must be set to validate the remaining bits
in the DTE and PTE. If either of the present bits are not
set, a page fault is generated when the DTE or PTE is
accessed. If P = 0, the remaining DTE/PTE bits are avail-
able for use by the operating system. For example, the
operating system can use these bits to record where on
the hard disk the pages are located. A page fault is also
generated if the memory reference violates the page pro-
tection attributes.
Since the page directory table can point to 1 K page
tables, and each page table can point to 1 K page frames,
a total of 1 M page frames can be implemented. Since
each page frame contains 4 KB, up to 4 GB of virtual
memory can be addressed by the CPU with a single page
directory table.
Translation Look-Aside Buffer
The translation look-aside buffer (TLB) is a cache for the
paging mechanism and replaces the two-level page table
lookup procedure for TLB hits. The TLB is a four-way set
associative 32-entry page table cache that automatically
keeps the most commonly used page table entries in the
processor. The 32-entry TLB, coupled with a 4 K page
size, results in coverage of 128 KB of memory addresses.
Along with the base address of the page table or the page
frame, each directory table entry or page table entry con-
tains attribute bits and a present bit as illustrated in Table
3-28.
The TLB must be flushed when entries in the page tables
are changed. The TLB is flushed whenever the CR3 regis-
ter is loaded. An individual entry in the TLB can be flushed
using the INVLPG instruction.
If the present bit (P) is set in the DTE, the page table is
present and the appropriate page table entry is read. If P
= 1 in the corresponding PTE (indicating that the page is
in memory), the accessed and dirty bits are updated, if
necessary, and the operand is fetched. Both accessed
bits are set (DTE and PTE), if necessary, to indicate that
the table and the page have been used to translate a linear
address. The dirty bit (D) is set before the first write is made
to a page.
DTE Cache
The DTE cache caches the two most recent DTEs so that
future TLB misses only require a single page table read to
calculate the physical address. The DTE cache is dis-
abled following reset and can be enabled by setting the
DTE_EN bit in CCR4[4] (Index E8h).
Table 3-28. Directory Table Entry (DTE) and Page Table Entry (PTE)
Bit
Name
Description
31:12
BASE
Base Address: Specifies the base address of the page or page table.
ADDRESS
11:9
8:7
6
AVAILABLE
RSVD
D
Available: Undefined and Available to the Programmer
Reserved: Unavailable to programmer
Dirty Bit:
PTE format — If = 1: Indicates that a write access has occurred to the page.
DTE format — Reserved.
5
4:3
2
A
Accessed Flag: If set, indicates that a read access or write access has occurred to the page.
RSVD
U/S
Reserved: Set to 0.
User/Supervisor Attribute:
If = 1: Page is accessible by User at privilege level 3.
If = 0: Page is accessible by Supervisor only when CPL ≤ 2.
1
0
W/R
P
Write/Read Attribute:
If = 1: Page is writable.
If = 0: Page is read only.
Present Flag:
If = 1: The page is present in RAM and the remaining DTE/PTE bits are validated
If = 0: The page is not present in RAM and the remaining DTE/PTE bits are available for use by the pro-
grammer.
Revision 3.1
73
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