Processor Programming (Continued)
3.7.3.2 Task, Gate and Interrupt Descriptors
The IDT descriptor table is defined by the Interrupt
Descriptor Table Register (IDTR). Some texts refer to this
register as an IDT descriptor.
Besides segment descriptors there are descriptors used
in task switching, switching between tasks with different
priority and those used to control interrupt functions:
The following instructions are used in conjunction with the
IDTR registers:
•
•
•
Task State Segment Table Descriptors
Gate Table Descriptors
Interrupt Descriptors.
•
•
LIDT - Load memory to IDTR
SIDT - Store IDTR to memory
All descriptors have some things in common. They are all
eight bytes in length and have three fields (BASE, LIMIT
and TYPE). The BASE field defines the starting location
for the table or segment. The LIMIT field defines the size
and the TYPE field depends on the type of descriptor.
One of the main functions of the TYPE field is to define
the access rights to the associated segment or table.
The IDTR is set up in REAL mode using the LIDT instruc-
tion. This is possible as the LIDT instructions is only one
of two instructions that directly load a linear address
(instead of a segment relative address) in protective
mode.
As previously shown in Table 3-20, the IDTR contains a
BASE ADDRESS field and a LIMIT field that define the
IDT tables.
Interrupt Descriptor Table
The Interrupt Descriptor Table is an array of 256 8-byte (4-
byte for real mode) interrupt descriptors, each of which is
used to point to an interrupt service routine. Every inter-
rupt that may occur in the system must have an associ-
ated entry in the IDT. The contents of the IDTR are
completely visible to the programmer through the use of
the SIDT instruction.
3.7.4 Descriptor Bit Structure
The bit structure for application and system descriptors is
shown in Table 3-21. The explanation of the TYPE field is
shown in Table 3-23 on page 68.
Table 3-21. Application and System Segment Descriptors
31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Memory Offset +4
9
8
7
6
5
4
3
2
1
0
BASE[31:24]
G
D
0
A
V
L
LIMIT[19:16]
P
DPL
S
TYPE
BASE[23:16]
Memory Offset +0
BASE[15:0]
LIMIT[15:0]
Table 3-22. Application and System Segment Descriptors Bit Definitions
Memory
Bit
Offset
Name
Description
31:24
7:0
+4
+4
+0
+4
+0
BASE
Segment Base Address: Three fields which collectively define the base location for the segment in
4 GB physical address space.
31:16
19:16
15:0
LIMIT
Segment Limit: Two fields that define the size of the segment based on the Segment Limit
Granularity Bit.
If G = 1: Limit value interpreted in units of 4 KB.
If G = 0: Limit value is interpreted in bytes.
23
22
+4
+4
G
D
Segment Limit Granularity Bit: Defines LIMIT multiplier.
If G = 1: Limit value interpreted in units of 4 KB. Segment size ranges from 1 byte to 1 MB.
If G = 0: Limit value is interpreted in bytes. Segment size ranges from 4 KB to 4 GB.
Default Length for Operands and Effective Addresses:
If D = 1: Code segment = 32-bit length for operands and effective addresses
If D = 0: Code segment = 16-bit length for operands and effective addresses
If D = 1: Data segment = Pushes, calls and pop instructions use 32-bit ESP register
If D = 0: Data segment = Stack operations use 16-bit SP register
20
+4
AVL
Segment Available: This field is available for use by system software.
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