Electrical Specifications (Continued)
t7
t8
DCLK
Figure 7-2. DCLK Timing and Measurement Points
t9
t10
V
IH (Min)
1.5V
V
IL (Max)
SDCLK,
SDCLK[3:0]
t13
t11
t12
Figure 7-3. SDCLK, SDCLK[3:0] Timing and Measurement Points
Table 7-8. System Signals
Parameter
Min
Max
Unit
Notes
Setup Time for RESET, INTR
Hold Time for RESET, INTR
Setup Time for SMI#, SUSP#, FLT#
Hold Time for SMI#, SUSP#, FLT#
Valid Delay for IRQ13, SUSPA#
Valid Delay for SERIALP
5
2
5
2
2
2
ns
ns
ns
ns
ns
ns
Note
Note
15
15
Note: The system signals may be asynchronous. The setup/hold times are required for determining static
behavior.
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