Integrated Functions (Continued)
Table 4-30. Display Controller Configuration and Status Registers (Continued)
Bit
Name
RTPM
Description
19
Real-Time Performance Monitoring: Allows real-time monitoring of a variety of internal GXm
processor signals by multiplexing the signals onto the CLKWR and DACRS[2:0] pins:
0 = Disable (Normal operation); 1 = Enable.
The CLKWR pin should not be fed to a clock chip or SYNDAC when this mode of operation is used, a dif-
ferent programming scheme should be used for the clock chip using the DACRS[2:0] signals and RAM-
DACRD# and RAMDACWR# signals. The selection of output signals is made using bits [27:16] of the
DC_BUF_SIZE register. The lower 12 bits of this field will select one of eight outputs for each pin.
18
FDTY
Frame Dirty Mode: Allow entire frame to be flagged as dirty whenever a pixel write occurs to the frame
buffer (this is provided for modes that use a linearly mapped frame buffer for which the line delta is not
equal to 1024 or 2048 bytes): 0 = Disable; 1 = Enable.
When disabled, dirty bits are set according to the Y address of the pixel write.
Reserved: Set to 0.
17
16
RSVD
CMPI
Compressor Insert Mode: Insert one static frame between update frames: 0 = Disable; 1 = Enable.
An update frame is referred to as a frame in which dirty lines will be allowed to be updated. Conversely, a
static frame is referred to as a frame in which dirty lines will not be updated (although the image may not
be static, since lines that are not compressed successfully must be retrieved from the uncompressed
frame buffer).
15:12
11:8
7:6
DFIFO
Display FIFO High Priority End Level: This field specifies the depth of the display FIFO (in 64-bit entries
HI-PRI END x 4) at which a high-priority request previously issued to the memory controller will end. The value is
LVL
dependent upon display mode.
This register should always be non-zero and should be larger than the start level.
DFIFO
HI-PRI
START LVL
Display FIFO High Priority Start Level: This field specifies the depth of the display FIFO (in 64-bit entries
x 4) at which a high-priority request will be sent to the memory controller to fill up the FIFO. The value is
dependent upon display mode.
This register should always be nonzero and should be less than the high-priority end level.
DCLK_
MUL
DCLK Multiplier: This 2-bit field specifies the clock multiplier for the input DCLK pin. After the input clock
is optionally multiplied, the internal DOTCLK, PCLK, and FPCLK may be divided as necessary.
00 = Forced Low
01 = 1 x DCLK
10 = 2 x DCLK
11 = 4 x DCLK
5
DECE
Decompression Enable: Allow operation of internal decompression hardware:
0 = Disable; 1 = Enable.
4
3
CMPE
PPC
Compression Enable: Allow operation of internal compression hardware: 0 = Disable; 1 = Enable
Pixel Panning Compatibility: This bit has the same function as that found in the VGA.
Allow pixel alignment to change when crossing a split-screen boundary - it will force the pixel alignment to
be 16-byte aligned: 0 = Disable; 1 = Enable.
If disabled, the previous alignment will be preserved when crossing a split-screen boundary.
2
DVCK
Divide Video Clock: Selects frequency of VID_CLK pin:
0 = VID_CLK pin frequency is equal to one-half (½) the frequency of the core clock.
1 = VID_CLK pin frequency is equal to one-fourth (¼) the frequency of the core clock.
Note: Bit 28 (VIDE) must be set to 1 for this bit to be valid.
1
0
CURE
DFLE
Cursor Enable: Allow operation of internal hardware cursor: 0 = Disable; 1 = Enable.
Display FIFO Load Enable: Allow the display FIFO to be loaded from memory:
0 = Disable; 1 = Enable.
If disabled, no write or read operations will occur to the display FIFO.
If enabled, a flat panel should be powered down prior to setting this bit low. Similarly, if active, a CRT
should be blanked prior to setting this bit low.
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