Connection Diagram
20049411
14-Lead Plastic TSSOP
θJA = 155˚C/W
NS Package Number MTC14
EAO (Pin 8) - Output of the error amplifier. The voltage level
Pin Description
on this pin is compared with an internally generated ramp
signal to determine the duty cycle. This pin is necessary for
compensating the control loop.
BOOT (Pin 1) - Supply rail for the N-channel MOSFET gate
drive. The voltage should be at least one gate threshold
above the regulator input voltage to properly turn on the
high-side N-FET.
SS (Pin 9) - Soft start pin. A capacitor connected between
this pin and ground sets the speed at which the output
voltage ramps up. Larger capacitor value results in slower
output voltage ramp but also lower inrush current.
LG (Pin 2) - Gate drive for the low-side N-channel MOSFET.
This signal is interlocked with HG to avoid shoot-through
problems.
FB (Pin 10) - This is the inverting input of the error amplifier,
which is used for sensing the output voltage and compen-
sating the control loop.
PGND (Pins 3, 13) - Ground for FET drive circuitry. It should
be connected to system ground.
SGND (Pin 4) - Ground for signal level circuitry. It should be
connected to system ground.
FREQ (Pin 11) - The switching frequency is set by connect-
ing a resistor between this pin and ground.
VCC (Pin 5) - Supply rail for the controller.
SD (Pin 12) - IC Logic Shutdown. When this pin is pulled low
the chip turns off the high side switch and turns on the low
side switch. While this pin is low, the IC will not start up. An
PWGD (Pin 6) - Power Good. This is an open drain output.
The pin is pulled low when the chip is in UVP, OVP, or UVLO
mode. During normal operation, this pin is connected to VCC
or other voltage source through a pull-up resistor.
internal 20µA pull-up connects this pin to VCC
.
HG (Pin 14) - Gate drive for the high-side N-channel MOS-
FET. This signal is interlocked with LG to avoid shoot-
through problems.
ISEN (Pin 7) - Current limit threshold setting. This sources a
fixed 50µA current. A resistor of appropriate value should be
connected between this pin and the drain of the low-side
FET.
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