Functional Description (Continued)
The ECL outputs have no pull-down resistors and can drive
series or parallel terminated transmission lines. For short
interconnections that do not require impedance matching, a
be connected together as close to the package as possible.
Pin 12 must always be connected to the V side of the
EE
supply, while pin 13 is required only if the TTL output is
used. Low impedance V and V distribution and RF by-
270X to 510X resistor to V can be used to establish the
EE
CC EE
V
level. Both V
pins must always be used and should
CC
pass capacitors are recommended to prevent crosstalk.
OL
Logic Diagram 11C90
TL/F/9892–6
Note: This diagram is provided for understanding of logic operation only. It should not be used for evaluation of propagation delays as many internal functions are
achieved more efficiently than shown.
Count Sequence Table 11C90
Operating Mode Table 11C90
Inputs
Output
Response
MS
CE
M
1
M
2
H
L
L
L
L
X
H
L
X
X
L
X
X
L
Set HIGH
Hold
d
d
d
11
10
10
L
H
X
X
H
L
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Don’t Care
X
TL/F/9892–7
Note: A HIGH on MS forces all Qs HIGH.
7