Functional Description
While the clock is LOW, the slave is held steady and the
information on the D input is permitted to enter the master.
The next transition from LOW to HIGH locks the master in
its present state making it insensitive to the D input. This
transition simultaneously connects the slave to the master
causing the new information to appear on the outputs. Mas-
ter and slave clock thresholds are internally offset in oppo-
site directions to avoid race conditions or simultaneous
master-slave changes when the clock has slow rise or fall
times.
The CP and CE inputs are logically identical, but physical
constraints associated with the Dual-In-Line package make
the CE input slower at the upper end of the toggle range. To
prevent new data from entering the master on the next CP
LOW cycle, CE should go HIGH while CP is still HIGH.
TL/F/9890–4
e
e
R
50X termination of scope
50X impedance lines
T
L
1
g
All input transition times are 2.0 ns 0.2 ns
FIGURE 1. Propagation Delay (CP to Q)
TL/F/9890–5
e
e
R
50X termination of scope
50X impedance lines
T
L
1
a
Adjust V for 0.7V baseline of
BIAS
800 mV peak-to-peak sinewave input.
g
All input transition times are 2.0 ns 0.2 ns
FIGURE 2. Toggle Frequency Test Circuit
3
NSC [ National Semiconductor ]
