100355 Low Power Quad Multiplexer/Latch
August 1998
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which
can accept and store data from two sources. When both En-
able (E
n
) inputs are LOW, the data that appears at an output
is controlled by the Select (S
n
) inputs, as shown in the Oper-
ating Mode table. In addition to routing data from either D
0
or
D
1
, the Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are LOW) and
can steer a HIGH signal from either D
0
or D
1
to an output.
The Select inputs can be tied together for applications re-
quiring only that data be steered from either D
0
or D
1
. A
positive-going signal on either Enable input latches the out-
puts. A HIGH signal on the Master Reset (MR) input over-
rides all the other inputs and forces the Q outputs LOW. All
inputs have 50 kΩ pulldown resistors.
Features
n
n
n
n
n
Greater than 40% power reduction of the 100155
2000V ESD protection
Pin/function compatible with 100155
Voltage compensated operating range = −4.2V to −5.7V
Standard Microcircuit Drawing
(SMD) 5962-9165401
Logic Symbol
DS100294-1
Pin Names
E
1
, E
2
S
0
, S
1
MR
D
na
–D
nd
Q
a
–Q
d
Q
a
–Q
d
Description
Enable Inputs (Active LOW)
Select Inputs
Master Reset
Data Inputs
Data Outputs
Complementary Data Outputs
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100294-3
DS100294-2
© 1998 National Semiconductor Corporation
DS100294
www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
