Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100318-2
DS100318-1
Logic Diagram
DS100318-4
Truth Tables (Each Flip-flop)
Asynchronous Operation
Inputs
Outputs
Qn(t+1)
L
Dn
CPa
CPb
MR
Synchronous Operation
X
X
X
H
Inputs
Outputs
=
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Don’t Care
Dn
L
CPa
N
CPb
L
MR
L
Qn(t+1)
L
t
Time before CP positive transition
N
H
L
L
L
H
=
t+1 Time after CP positive transition
N =
LOW-to-HIGH transition
N
N
N
L
L
L
L
H
X
X
X
L
H
H
L
Qn(t)
Qn(t)
Qn(t)
N
H
L
L
L
L
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