100341 Low Power 8-Bit Shift Register
August 1998
100341
Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (P
n
) and outputs (Q
n
) for parallel op-
eration, and with serial inputs (D
n
) and steering logic for bidi-
rectional shifting. The flip-flops accept input data a setup
time before the positive-going transition of the clock pulse
and their outputs respond a propagation delay after this ris-
ing clock edge.
The circuit operating mode is determined by the Select in-
puts S
0
and S
1
, which are internally decoded to select either
“parallel entry”, “hold”, “shift left” or “shift right” as described
in the Truth Table. All inputs have 50 kΩ pull-down resistors.
Features
n
n
n
n
n
35% power reduction of the 100141
2000V ESD protection
Pin/function compatible with 100141
Voltage compensated operating range = −4.2V to −5.7V
Standard Microcircuit
Drawing (SMD) 5962-9459101
Logic Symbol
CP
Pin Names
S
0
, S
1
D
0
, D
7
P
0
–P
7
Q
0
–Q
7
DS100315-1
Description
Clock Input
Select Inputs
Serial Inputs
Parallel Inputs
Data Outputs
© 1998 National Semiconductor Corporation
DS100315
www.national.com
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