SM6802A
BLOCK DIAGRAM
LEQP LEQN TESTN DRCN PWDN MUTEN
VDD3
−
LIN
BUFFER
BUFFER
LEVEL SHIFTER
LOUTP
LOUTN
+
PWM
Modulator
LEVEL SHIFTER
−
+
MUTE,POWERDOWN,
PROTECTION
BIAS
VREF
VREF1
RIN
OSC
VSS2
−
+
BUFFER
BUFFER
LEVEL SHIFTER
LEVEL SHIFTER
ROUTP
REQP
REQN
PWM
Modulator
−
ROUT
+
VSS1 VDD1
VDD2
PIN DESCRIPTION
*1
*2
Number
Name
LEQP
LIN
I/O
Function
1
2
I
I
Lch equalizer network connection
Lch signal input
3
VDD1
RIN
–
I
Supply (input system)
4
Rch signal input
5
REQP
REQN
VSS1
I
Rch equalizer network connection
Rch equalizer network connection
Ground (input system)
6
I
7
–
I
8
PDWN
DRCN
ROUTN
VDD2
ROUTP
VSS2
Power-down control (active LOW)
9
I
Dynamic range compression mode setting (HIGH: normal operation, LOW: compression mode)
Rch speaker minus (–) output
10
11
12
13
14
15
16
17
18
19
20
O
–
Supply (output stage)
O
–
Rch speaker plus (+) output
Ground (output stage)
LOUTP
VDD3
LOUTN
MUTEN
TESTN
VREF1
LEQN
O
–
Lch speaker plus (+) output
Supply (output stage)
O
I
Lch speaker minus (–) output
Mute control (active LOW)
Ip
–
Test pin (HIGH: normal operation, LOW: test mode)
Reference voltage 1 (bias voltage)
Lch equalizer network connection
O
*1. V
= VDD1, V
*2. Ip = input pin with built-in pull-up resistor
= VDD2 = VDD3, V = VSS1 = VSS2
DDP SS
DDS
NIPPON PRECISION CIRCUITS INC.—2
NPC [ NIPPON PRECISION CIRCUITS INC ]
