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SM5843AP1 参数 Datasheet PDF下载

SM5843AP1图片预览
型号: SM5843AP1
PDF下载: 下载PDF文件 查看货源
内容描述: 音频多功能数字滤波器 [Audio Multi-function Digital Filter]
分类和应用: 外围集成电路光电二极管LTE
文件页数/大小: 24 页 / 263 K
品牌: NPC [ NIPPON PRECISION CIRCUITS INC ]
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SM5843A×1  
PIN DESCRIPTION  
1
Number  
Name  
DI/INF2N  
BCKI  
I/O  
Description  
1
2
3
Ip  
Ip  
Ip  
Data input when INF1N is LOW, and input format select pin when INF1N is HIGH.  
Input bit clock  
CKSLN  
Oscillator and system clock select input. 384fs when HIGH, and 256fs when LOW.  
Input format select pin. INF1N and INF2N select the pin functions below.  
Pin function selection  
INF1N  
DI/INF2N  
Input format  
DI/INF2N IW1N/DIL IW2N/DIR  
LOW  
LOW  
HIGH  
HIGH  
LOW  
HIGH  
LOW  
HIGH  
4
INF1N  
Ip  
LR alternating, trailing data  
DI  
IW1N  
DIL  
IW2N  
DIR  
LR alternating, leading data  
LR simultaneous, leading data  
INF2N  
Input bit length select pin when INF1N is LOW, and left-channel data input when INF1N is HIGH.  
IW1N and IW2N select the input data length.  
INF1N  
IW2N/DIL  
LOW  
LOW  
HIGH  
HIGH  
×
IW1N/DIR  
LOW  
HIGH  
LOW  
HIGH  
×
Input bit length  
20 bits  
5
IW1N/DIL  
Ip  
20 bits  
LOW  
18 bits  
16 bits  
HIGH  
20 bits  
6
7
8
9
XTI  
XTO  
VSS  
CKO  
I
Oscillator input connection  
Oscillator output connection  
Ground  
O
O
Oscillator output clock. Same frequency as XTI.  
Input bit length select pin when INF2N is LOW, and right-channel data input when INF2N is HIGH.  
IW1N and IW2N select the input data length as shown in the table for pin 5.  
10  
IW2N/DIR  
Ip  
11  
12  
13  
14  
15  
16  
MDT  
MCK  
Ip  
Ip  
Ip  
Ip  
Ip  
Ip  
Attenuator serial data input  
Attenuator bit clock input  
MLEN  
RSTN  
MUTE  
DEMP  
Attenuator latch enable input  
System reset. Reset operation when LOW, and normal operation when HIGH.  
Mute control signal. Muting when HIGH, and normal operation when LOW.  
Deemphasis control signal. OFF when LOW, and ON when HIGH.  
Deemphasis lter select inputs  
FSEL1  
LOW  
LOW  
HIGH  
HIGH  
FSEL2  
LOW  
HIGH  
LOW  
HIGH  
Sampling frequency (fs)  
44.1 kHz  
17  
18  
FSEL1  
FSEL2  
Ip  
Ip  
48 kHz  
Test mode  
32 kHz  
19  
20  
21  
22  
OW20N  
SYNCN  
TMOD1  
VDD  
Ip  
Ip  
Ip  
Output bit length select pin. 20-bit output when LOW, and 18-bit output when HIGH.  
Sync mode select pin. Normal sync mode when LOW, and jitter-free mode when HIGH.  
Dither processing control. ON when LOW, and OFF when HIGH.  
5 V supply  
NIPPON PRECISION CIRCUITS—4