5075 series
PAD LAYOUT
(Unit: µm)
ꢀ 5075A× (for Flip Chip Bonding)
ꢀ 5075B× (for Wire Bonding)
(420, 345)
Q
(420, 345)
VSS
VSS
Q
5
5
6
4
3
4
3
Y
Y
VC
VDD
VDD
6
VC
(0,0)
(0,0)
1
2
1
2
(−420, −345)
(−420, −345)
XT
XTN
XTN
XT
X
X
Chip size: 0.84 × 0.69mm
Chip thickness: 130µm 15µm
Chip size: 0.84 × 0.69mm
Chip thickness: 130µm 15µm
PAD size: 90µm × 90µm
Chip base: V level
SS
PAD size: 90µm × 90µm
Chip base: V level
SS
PAD DIMENSIONS PIN DESCRIPTION
Pad dimensions [µm]
Pad No.
Pad No.
Pin
I/O
Description
X
Y
5075A× 5075B×
1
2
3
4
5
–189
189
315
315
–315
–240
–240
–21
225
225
1
2
3
4
5
2
1
6
5
4
XT
XTN
VDD
Q
I
Crystal connection pin (amplifier input)
O
–
Crystal connection pin (amplifier output)
(+) supply pin
O
–
Clock output pin
VSS
(−) supply pin
Oscillation frequency control voltage input pin (positive polarity)
(frequency increases with increasing voltage)
6
–315
–21
6
3
VC
I
BLOCK DIAGRAM
Voltage
Regulator
Rf
VDD
CIN
Oscillation
Detector
XT
RD
COUT
Level Shifter
XTN
RVC2
CMOS ouput
Buffer
1
N*1
Q
RVC1
VC
CVC1
CVC2
VSS
*1. N = 1, 2, 4, 8, 16
SEIKO NPC CORPORATION —3