CF5018 series
PAD LAYOUT
(Unit:
µ
m)
(720,730)
VDD
HA5018
NPC
Q
VSS
Y
INHN
(0,0)
XT
X
XTN
Chip size: 0.72
×
0.73mm
Chip thickness: 220 ± 30µm
PAD size: 90µm
Chip base: V
DD
level
PIN DESCRIPTION and PAD DIMENSIONS
Pad dimensions [µm]
Name
I/O
Description
X
INHN
XT
XTN
VSS
Q
VDD
I
I
O
–
O
–
Output state control input. High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
Amplifier input
Amplifier output
Ground
Output. Output frequency. High impedance in standby mode
Supply voltage
Crystal connection pins.
Crystal is connected between XT and XTN.
151
238
503
588
588
131
Y
277
131
131
345
598
598
BLOCK DIAGRAM
VDD VSS
XTN
C
G
R
f1
C
f
C
D
XT
R
f2
Q
INHN
INHN = LOW active
SEIKO NPC CORPORATION —2
NPC [ NIPPON PRECISION CIRCUITS INC ]
