CF5017 series
PAD LAYOUT
(Unit: µm)
(720,730)
Q
VDD
INHN
(0,0)
NPC
VSS
Y
XT XTN
X
Chip size: 0.72 × 0.73mm
Chip thickness: 220 30ꢀm
PAD size: 90ꢀm
Chip base: V level
DD
PIN DESCRIPTION and PAD DIMENSIONS
Pad dimensions [µm]
Name
I/O
Description
X
Y
Output state control input. High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
INHN
I
151
277
XT
XTN
VSS
Q
I
Amplifier input
238
503
588
588
131
131
131
345
598
598
Crystal connection pins.
Crystal is connected between XT and XTN.
Amplifier output
O
–
Ground
O
–
Output. Output frequency. High impedance in standby mode
Supply voltage
VDD
BLOCK DIAGRAM
VDD VSS
XTN
XT
C
G
C
D
R
f1
f2
Cf
Q
R
INHN
INHN = LOW active
SEIKO NPC CORPORATION —2
NPC [ NIPPON PRECISION CIRCUITS INC ]
