5087 series
PAD LAYOUT
(Unit: m)
VCC2
(600,550)
OE
OUT OUTN
VCC2
11
10
9
7
8
(0,0)
Y
VCC1
(-600,-550)
1
GND2
6
2
3
4
5
VCC1 XIN XOUT GND1
X
Chip size: 1.20mm×1.10mm
Chip thickness: 180m , 300m
PAD size: 80m×80m(PAD No.2, 3, 4, 5, 7, 9 pins)
80m×150m(PAD No.6, 8 pins)
110m×80m(PAD No.10, 11 pins)
80m×134m(PAD No.1 pin)
Chip base: GND potential
PIN DESCRIPTION and PAD COORDINATES
PAD coordinate [m]
No.
Name
i/o*1
Function
X
Y
1
2
3
4
5
6
VCC1*2
VCC1*2
XIN
-
-
i
-395
-290
-72
-424
-440
-440
-440
-440
-440
(+) supply pin (for oscillation circuit)
Oscillator input pin
Oscillator output pin
XOUT
GND1*3
GND2*3
o
-
-
107
290
395
(-) ground pin (for oscillation circuit)
(-) ground pin (for all circuits excluding oscillation circuit)
Output enable pin. Outputs are high impedance when LOW
(oscillator stopped). Power-saving pull-up resistor built-in.
7
OE
i
377
440
8
VCC2*2
VCC2*2
OUTN
OUT
-
-
190
85
440
440
440
440
(+) supply pin (for all circuits excluding oscillation circuit)
9
LVDS complementary output pin. Disable: High impedance
LVDS output pin. Disable: High impedance
10
o
o
-114
-380
11
*1. i: input, o: output
*2. Connect both of pins by wire-bonding for good characteristics.
*3. GND1 and GND2 pins should be connected by wire-bonding since they are disconnected.
SEIKO NPC CORPORATION - 2