5042 series
PAD LAYOUT
(Unit:
µ
m)
(420,345)
Q
Y
VDD
5
6
1
(−420,−345)
XTN
X
(0,0)
2
XT
4
3
VSS
INHN
Chip size: 0.84mm
×
0.69mm
Chip thickness: 130
µ
m
±
15
µ
m
Pad size: 80
µ
m
×
80
µ
m
Chip base: V
SS
level
PAD DIMENSIONS
Pad No.
1
2
3
4
5
6
Pin
XTN
XT
INHN
VSS
Q
VDD
I/O
O
I
I
–
O
–
PIN DESCRIPTION
Pad dimensions [µm]
Name
Amplifier output
Amplifier input
Output state control input
(–) ground
Output
(+) supply voltage
Description
X
Crystal connection pins.
Crystal is connected between XT and XTN.
High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
–
Output frequency determined by internal circuit
to one of f
O
, f
O
/2, f
O
/4, f
O
/8, f
O
/16, f
O
/32.
High impedance in standby mode
–
–225.2
225.2
328.5
328.5
–328.5
–328.5
Y
–253.5
–253.5
–5.0
223.8
223.8
–5.0
BLOCK DIAGRAM
XT
R
V
R
F
R
V
Regulator
*2
1
N
*1
Oscillation
Detection
XTN
VDD
Q
INHN
Temperature
Compensation
VSS
Control Register
FO, TO, RTG, TLO, TLG,
THO, THG
*1. N = 1, 2, 4, 8, 16, 32 (mask option)
*2. 5042A×A version only
SEIKO NPC CORPORATION—3
NPC [ NIPPON PRECISION CIRCUITS INC ]
