NJG1707PG1
nTERMINAL
INFORMATION
PIN NO.
4
5
6
7
SYMBOL
CTL1
CTL2
CTL3
V
SS
DESCRIPTIONS
Control signal input terminal of high impedance C-MOS logic. Logic level: High; more
than +2V, Low; 0~+0.6V. Please connect to GND or V
DD
with 100kΩ if potential is
open or uncertain.
Negative supply terminal. Negative voltage of -3.5~-2.0V must be supplied on Tx
mode. This terminal is isolated on Rx mode, so open or –2.5~0V condition can be
used. Please connect bypass capacitor with GND to keep RF performance.
Positive supply terminal. The voltage of this terminal should be supplied before or
same time with other DC supplying terminals (CTL1~3, V
SS
). The bias voltage should
be +2.7~+5.0V. Please connect bypass capacitor with GND to keep RF performance.
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
Tx power input terminal. A DC cut capacitor is required to block V
DD
voltage, and also
an external matching circuit is required to improve VSWR(See Application circuit).
A termination terminal for ANT1 in case ANT2 is in use. The influence of ANT1
against ANT2 is reduced. A DC cut capacitor (10pF) is required to block V
DD
voltage.
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
Rx output terminal. A DC cut capacitor is required to block V
DD
voltage, and also an
external matching circuit is required to improve VSWR(See Application circuit).
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
A termination terminal for ANT2 in case ANT1 is in use. The influence of ANT2
against ANT1 is reduced. A DC cut capacitor (10pF) is required to block V
DD
voltage.
Ground terminal of LNA. Please place ground plane close to this pin for good RF
performance.
LNA input terminal. An external matching circuit is required.
LNA output terminal. An external matching circuit with LNA biasing element L3, L4 as
in application circuit is required.
Bypass capacitor terminal of LNA. Please place C9 as in application circuit close to
this terminal.
Ground terminal. Please connect to ground plane as close as possible for good RF
performance.
9
11
13
15
17
19
21
23
25
26,27
28
30
31
1,2,3,8,10,
12,14,16,1
8,20,22,24,
29,32
V
DD
EXT2
EXT1
TX
TER2
ANT1
RX
ANT2
TER1
GND(LNA)
LNAIN
LNAOUT
EXTCAP
GND
nTRUTH
TABLE
”H”=V
CTL (H)
, ”L”=V
CTL (L)
, ”X”=H or L
CONTROL INPUT
ROUTE
Tx-ANT1
Tx-EXT1
Rx-ANT1
Rx-ANT2
Rx-EXT1
Rx-EXT2
Tx/Rx
CTL1
H
H
L
L
L
L
Diversity IN/OUT
CTL2
X
X
L
H
L
H
CTL3
H
L
H
H
L
L
CONTROL OUTPUT
SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9
OFF OFF OFF
OFF OFF
OFF OFF
ON
OFF
ON
ON
ON
OFF
OFF
ON
ON
ON
ON
ON
ON
OFF OFF OFF
ON
OFF
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF OFF
OFF OFF OFF OFF
ON
OFF OFF
OFF OFF OFF
-5-
NJRC [ NEW JAPAN RADIO ]
