NJG1655ME7
I
APPLICATION CIRCUIT
(TOP VIEW)
0/1.8V
0/1.8V
C8
P3A
18
1
C7
P3B
17
VCTL1
16
VCTL2
15
14
2
DECODER
VDD
13
C9
C1
P2A
3
12
2.7V
C6
PCA
C2
P2B
4
11
C5
PCB
5
6
P1B
7
P1A
8
9
10
C3
C4
I
PARTS LIST
PART ID
C1~C8
C9
I
TEST PCB LAYOUT
(TOP VIEW)
P3A
P3B
Value
56pF
1000pF
Notes
MURATA
(GRM15)
Losses of PCB, capacitors and connectors
P2A
C8
VCTL1
C7 VCTL2
VDD
C9
C6
C2
C3
C4
C5
PCA
Frequency
1GHz
2GHz
Loss
0.36dB
0.49dB
C1
P2B
PCB
P1A
P1B
PRECAUTIONS
[1] The DC blocking capacitors (C1~C8) must be placed at all RF terminals (PCA, PCB, P1A, P1B, P2A,
P2B, P3A and P3B).
[2] The bypass capacitor (C9) should be placed as close as VDD terminal.
[3] Please layout ground pattern right under this IC to avoid degradation of isolation or high power
characteristics.
-8-
NJRC [ NEW JAPAN RADIO ]
