NJG1683ME7
I TEST PCB LAYOUT
(TOP VIEW)
P3A
P3B
PCB:
FR-4, t=0.2mm
Capacitor Size: 1005
Strip Line Width: 0.4mm
VCTL1
PCB Size:
26 x 26mm
C7
C8
P2A
PCA
VCTL2
VDD
Losses of PCB, capacitors and connectors
C9
C1
C6
C5
Frequency (GHz)
Loss (dB)
0.33
1.0
2.0
2.7
C2
0.57
C3
C4
0.71
P2B
PCB
P1B
<PCB LAYOUT GUIDELINE>
P1A
14 13 12 11 10
15
PCB Pattern
9
8
7
6
Through-hole (radius: 0.10mm)
Pin
16
17
18
Note2:
The ground plane and the through-holes under Tab, as shown
in the picture, are not necessities. There is no problem in deleting
them in the practical PCB design, though in such case beware
that the GND terminals (pin 1, 2, 8, 9 and 10 as for this particular
design shown in the picture) still need through-holes being
located in their vicinities.
1
2
3
4
5
PRECAUTIONS
[1] The DC current at RF ports must be equal to zero, which can be achieved with DC blocking capacitors
(C1~C8).
(However, in case there is no possibility that DC current flows, the DC blocking capacitors are unnecessary, e.g.
the RF signals are fed by SAW filters that block DC current by nature, etc.)
[2] To reduce stripline influence on RF characteristics, please locate the bypass capacitor (C9) close to VDD
terminal.
[3] For good isolation, the GND terminals must be connected to the PCB ground plane of substrate, and the
through-holes connecting the backside ground plane should be placed near by the pin connection.
- 11 -
NJRC [ NEW JAPAN RADIO ]
