NJG1647HD3
! APPLICATION CIRCUIT
(TOP VIEW)
GND GND
L1
VDD=2.7V
CTL1
4
5
6
3
2
1
C4
P1
C2
CTL2
P2
C3
C1
GND
GND
! PARTS LIST
No.
Parameters
56pF
Note
C1~C3
Murata MFG
(GRM15)
C4
L1
1000pF
82nH
TDK (MLG0603)
! TEST PCB LAYOUT
(TOP VIEW)
P2
PCB SIZE=19.4x15.0mm
PCB: FR-4, t=0.2mm
CAPACITOR: size 1005
INDUCTOR: size 0603
C3
1pin mark
Strip Line Width=0.4mm(Zo=50Ω)
PC
P1
C1
C2
L1
! Losses of PCB
(Connector and DC blocking Capacitor
losses are included)
C4
Frequency
(GHz)
Loss (dB)
PC-P1
PC-P2
0.9
1.9
0.23
0.33
0.21
GND
CTL2 VDD CTL1
GND
0.30
PRECAUTIONS
[1]
[2]
The DC blocking capacitors have to be placed at RF terminal of PC, P1 and P2.
To control the influence on the RF performance, the terminal of VDD should be
connected with ground through the inductor L1 and the bypass capacitor C4.
[3]
For good RF performance, the ground terminals must be placed possibly close to ground plane
of substrate, and through holes for GND should be placed near by the pin connection.
- 10 -
NJRC [ NEW JAPAN RADIO ]
