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NJG1515AVB2-R2 参数 Datasheet PDF下载

NJG1515AVB2-R2图片预览
型号: NJG1515AVB2-R2
PDF下载: 下载PDF文件 查看货源
内容描述: TDMA天线开关的GaAs MMIC [TDMA ANTENNA SWITCH GaAs MMIC]
分类和应用: 开关
文件页数/大小: 18 页 / 549 K
品牌: NJRC [ NEW JAPAN RADIO ]
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NJG1515AVB2  
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TERMINAL INFORMATION  
PIN NO. SYMBOL  
DESCRIPTIONS  
1
2
3
CTL2  
CTL3  
VSS  
High-impedance C-MOS input terminal. This terminal is set to High-Level by  
2V~VDD, and Low-Level by +0.6V~0V. In case of open or unstable level,  
connect this terminal by 100KW resistor with GND terminal or VDD terminal.  
High-impedance C-MOS input terminal. This terminal is set to High-Level by  
2V~VDD, and Low-Level by +0.6V~0V. In case of open or unstable level,  
connect this terminal by 100KW resistor with GND terminal or VDD terminal.  
Negative voltage supply terminal. The negative voltage (-3.5~-2.0V) have to  
be supplied on transmitting. Otherwise negative voltage of -2.5~0V can be  
used or this terminal can be stayed open, because internal level of this  
terminal is automatically set to GND level on receiving. The bypass capacitor  
have to be connected with GND terminal for excellent RF performance.  
RF receiving port. An external capacitor of 56pF~100pF is required to block  
DC voltage (VDD).  
4
6
EXT2  
EXT1  
TX  
RF transmitting/receiving port. An external capacitor of 56pF~100pF is  
required to block DC voltage (VDD).  
8
RF transmitting port. An external capacitor of 56pF~100pF is required to  
block DC voltage (VDD).  
10  
TER2  
ANT1 termination port. The influence of ANT1 port to ANT2 port is  
suppressed by terminating this port by an appropriate termination. An  
external capacitor (5pF) is required to block DC voltage (VDD).  
RF transmitting/receiving port. An external capacitor of 56pF~100pF is  
required to block DC voltage (VDD).  
11  
13  
15  
17  
ANT1  
RX  
RF receiving port. An external capacitor of 56pF~100pF is required to block  
DC voltage (VDD).  
ANT2  
TER1  
RF receiving port. An external capacitor of 56pF~100pF is required to block  
DC voltage (VDD).  
ANT2 termination port. The influence of ANT2 port to ANT1 port is  
suppressed by terminating this port with appropriate termination. An external  
capacitor (5pF) is required to block DC voltage (VDD).  
19  
20  
VDD  
Positive voltage supply terminal. The positive voltage (2.7~5.0V) have to be  
supplied. The bypass capacitor have to be connected with GND terminal for  
excellent RF performance.  
CTL1  
GND  
High-impedance C-MOS input terminal. This terminal is set to High-Level by  
2V~VDD, and Low-Level by +0.6~0V. In case of open or unstable level,  
connect this terminal by 100kW resistor with GND terminal or VDD terminal.  
Ground terminal. Please connect this terminal with ground plane as close as  
possible for excellent RF performance.  
5,7,9,12,  
14,16,18  
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