NJG1104KB2
nTERMINAL
INFORMATION
Pin
1
2, 4
3
5
6
Description
This terminal is internally connected to FET’s source of LNA. Please connect self-
SOURCE bias resistor (R1) and bypass capacitor (C3) through source inductor (L5). NF and
IIP3 are tunable by C3 and L5.
GND
RFout
Ground (0V) terminal. Ground plane should be placed as close to the ground
terminals. .
RF output and drain voltage supplies terminal. External matching circuit is
required.
Function
VCONT Gain control voltage (V
CONT
) supplies terminal.
RFin
RF input terminal. External matching circuit and DC blocking capacitor are required.
-3-