100 MS/s, 16-Bit Arbitrary Waveform Generator
Specifications
Specifications are valid for 0 to 55 °C, unless otherwise noted.
Onboard Clock (Internal VCXO)
Sample clock source ........................................ Phase locked to reference clock or derived from onboard
VCXO frequency reference.
Frequency accuracy .......................................... ±25 ppm
PLL reference clock sources............................. PXI_CLK10, CLK IN, RTSI_7
General
Number of channels.........................................
DAC resolution .................................................
Maximum sampling rate ..................................
Maximum effective sampling rate
with Interpolation.............................................
Bandwidth ........................................................
Output paths.....................................................
1
16 bits
100 MS/s
400 MS/s
43 MHz
1. Main Output Path setting with driver selected Low
Gain Amplifier or the High Gain Amplifier
2. Direct Path optimized for IF applications
Digital Data and Control, DDC (optional front panel connector)
Data output signals.......................................... 16 LVDS data lines (ANSI/TIA/EIA-644 compliant)
Start Trigger
Sources ............................................................ PFI <0:3>, PXI_TRIG<0:7>, RTSI <0:7>
PXI Star Trigger, Software, Immediate
Modes............................................................... Single, Continuous, Stepped, Burst
Analog Output
Amplitude range (full scale)
Main output path .............................................
Direct path........................................................
Offset range .....................................................
Output impedance ............................................
DC Accuracy
0 to 55 ˚C ...................................................
Within ±10 ˚C of
self-calibration temperature .....................
AC amplitude accuracy ....................................
Output filters ....................................................
12 V
pp
to 5.64 mV
pp
(50
Ω
load)
1 V
pp
to 0.707 V
pp
(50
Ω
load)
±25% of Amplitude Range
50 or 75
Ω,
software selectable
±0.4% of amplitude, ±0.05% of offset ±1 mV
Markers
Destinations ..................................................... PFI <0:1>, PFI <4:5>, PXI_TRIG <0:7>, RTSI <0:7>
Quantity ............................................................ 1 Marker per Segment
Waveform and Instruction Memory Utilization
Onboard Memory Size
8 MB Standard
8,388,608 bytes
32 MB Option
33,554,432 bytes
256 MB Option
268,435,456 bytes
±0.2% of amplitude, ±0.05% of offset ±500
ΩV
± 1.0% of Amplitude ± 1 mV at 50 kHz
2. Software selectable seven-pole elliptical analog filter
and finite impulse response (FIR) digital interpolating filter
Passband flatness ............................................ ± 0.25 dB (100 Hz to 40 MHz) for Direct Path
Output modes ................................................... Arbitrary waveform; Arbitrary sequence
Loop count ........................................................ 1 to 16,777,215. Burst trigger: unlimited
Memory Limits
Arbitrary waveform
Mode maximum
Waveform memory
Arbitrary sequence
Mode maximum
Waveform memory
Arbitrary sequence
Mode maximum
Waveforms
Arbitrary sequence
Mode maximum
Segments in a sequence
8 MB
4,194,176
Samples
4,194,120
Samples
65,000
32 MB
16,777,088
Samples
16,777,008
Samples
262,000
256 MB
134,217,600
Samples
134,217,520
Samples
2,097,000
Comment
Refer to detailed
specifications for all
trigger modes.
Condition: One or
two segments
in a sequence
Condition: One or
two segments
in a sequence
Condition: Waveform
memory is
<4,000 samples.
Normalized Passband Flatness, Direct Path
104,000
418,000
3,354,000
Power
+3.3 VDC
1.9 A
+5 VDC
2.0 A
+12 VDC
0.46 A
-12 VDC
0.01 A
Total Power
21.9 W
Physical
Front panel connectors
CH0 ............................................................
CLK IN ........................................................
PFI 0 ...........................................................
PFI 1 ...........................................................
Digital data and control ...................................
SMB (Jack)
SMB (Jack)
SMB (Jack)
SMB (Jack)
68-pin VHDCI Female Receptacle
Rise/fall time.................................................... < 8 ns for Main Output Low Gain Path
Spectral Characteristics
Signal to Noise
and Distortion (SINAD)
Spurious Free Dynamic
Range w/ Harmonics
Spurious Free Dynamic
Range w/o Harmonics
Total Harmonic
Distortion (THD)
Frequency
1 MHz
10 MHz
1 MHz
10 MHz
1 MHz
10 MHz
20 kHz
1 MHz
Direct Path
Low Gain Path
Comments
64 dB
66 dB
Amplitude -1 dBFS
61 dB
60 dB
Measured from DC to
76 dBc
71 dBc
50 MHz
68 dBc
64 dBc
88 dBFS
91 dBFS
87 dBFS
-89 dBFS
-77 dBc (0.014%) -77 dBc (0.014%) Amplitude -1 dBFS
-75 dBc
-70 dBc
2nd through 6th
harmonics
Environment
Operating temperature (PXI) ............................
Operating temperature (PCI) ............................
Storage temperature ........................................
Relative humidity .............................................
0 to +55 °C (Meets IEC-60068-2-1 and IEC-60068-2-2)
0 to +45 °C
-25 to +85 °C (Meets IEC-60068-2-1 and IEC-60068-2-2)
10 to 90%, noncondensing (Meets IEC 60068-2-56)
Calibration
Self-calibration................................................. Correction for DC gain offset, and timing errors
External calibration interval............................. 2 years
Average Noise Density
Amplitude Range
Path
V
p-p
dBm
Low gain
0.1
-16.0
High gain
12
25.6
Average Noise Density
nV/√Hz
dBm/Hz dBfs/Hz
9
-148
-132.0
213
-120
-145.6
Certifications and Compliances
CE Mark compliance
Note
Unless otherwise noted, the following conditions were used for each specification:
A. Analog filter enabled
B. Interpolation set to maximum allowed factor for a given sample rate
C. Signals terminated with 50Ω
D. Direct path set to 1 Vpk-pk, Low Gain Amplifier Path set to 2 Vpk-pk,
and High Gain Amplifier Path set to 12 Vpk-pk
E. Sample clock set to 100 MS/s
For detailed specifications on power, environmental, safety, and physical dimensions, please visit
ni.com/products
and enter express code:
pxi5421
or
pci5421
Sample Clock
Sources ............................................................ Internal Divide-by-N, Internal High-Resolution, External CLK
IN, External DDC Clk In, PXI star Trigger, PXI_TRIG <0:7>,
RTSI <0:7>
Frequency resolution
Divide-by-N................................................ (100 MS/s) / N where 1
≤
N
≤
4,194,304
High Resolution ......................................... 1.06 µHz
System Phase
Noise Density
-137 dBc/Hz (10 kHz offset)
-137 dBc/Hz (10 kHz offset)
-126 dBc/Hz (10 kHz offset)
System Output
Jitter
< 1.0 ps rms
< 2.0 ps rms
< 4.0 ps rms
Comment
10 MHz carrier
Divide-by-N (PXI)
Divide-by-N (PCI)
High Resolution
National Instruments • Tel: (800) 433-3488 • Fax: (512) 683-9300 • info@ni.com • ni.com
3
NI [ NATIONAL INSTRUMENTS CORPORATION ]
