欢迎访问ic37.com |
会员登录 免费注册
发布采购

777741-01 参数 Datasheet PDF下载

777741-01图片预览
型号: 777741-01
PDF下载: 下载PDF文件 查看货源
内容描述: 高速电压输出 - 高达1 MS /秒/通道,多达16位,多达32个通道 [High-Speed Voltage Output- up to 1 MS/s/Channel, up to 16-Bit, up to 32 Channels]
分类和应用:
文件页数/大小: 8 页 / 444 K
品牌: NI [ NATIONAL INSTRUMENTS CORPORATION ]
 浏览型号777741-01的Datasheet PDF文件第1页浏览型号777741-01的Datasheet PDF文件第2页浏览型号777741-01的Datasheet PDF文件第3页浏览型号777741-01的Datasheet PDF文件第4页浏览型号777741-01的Datasheet PDF文件第6页浏览型号777741-01的Datasheet PDF文件第7页浏览型号777741-01的Datasheet PDF文件第8页  
High-Speed Voltage Output – up to
1 MS/s/Channel, up to 16-Bit, up to 32 Channels
Specifications – NI 671x and NI 673x
These specifications are typical at 25 °C unless otherwise stated.
Specifications – NI 672x
These specifications are typical at 25
o
C unless otherwise stated.
Analog Output
Output Characteristics
Number of channels
NI 6715/6713/6733 ................................... 8 voltage outputs
NI 6711/6731............................................. 4 voltage outputs
Resolution......................................................... 12 bits, 1 in 4,096 (NI 671x),
16 bits, 1 in 65,536 (NI 673x)
Number of
Channels
1
2
3
4
5
6
7
8
1
These
Analog Output
Output Characteristics
Number of channels
NI 6722 ...................................................... 8 voltage outputs
NI 6723 ...................................................... 32 voltage outputs
Resolution......................................................... 13 bits, 1 in 8,192
Max update rate
Number of Channels
1
2
8
16
24
32
1
These
Maximum Update Rate (NI 671x/673x)
Using Local
Using Host
FIFO (kS/s)
1
Memory (kS/s)
2
1,000
1,000
1,000
1,000
1,000
1,000
1,000
1,000
1,000
1,000
952
1,000
833
869
740
769
Max Update Rate (NI 6715)
Using Local
Using Host
FIFO (kS/s)
1
Memory (kS/s)
2
1,000
800
850
400
750
266
650
200
600
160
550
133
510
114
480
100
Max Update Rate (kS/s)
Using Local FIFO
1
Using Host PC Memory
2
800
800
714
714
476
182
333
90.9
253
60
204
45
numbers apply to continuous waveform generation, which allows for the time it takes to reset the FIFO to the
beginning when cycling through it. This additional time is not incurred when using host PC memory for waveform generation.
The max update rate in FIFO mode does not change regardless of the number of devices in the system.
2
These
numbers apply to continuous waveform generation, and do not change irrespective of the number of devices
in the system.
2
These numbers may change when using more devices or when other CPU or bus activity is taking place.
results were measured using an NI 6722/6723 device with a 550 MHz Pentium III machine. These numbers may
change when using more devices or when other CPU or bus activity occurs.
FIFO buffer size
NI 6713/6733.............................................
NI 6711/6715/6731 ...................................
Data transfers ..................................................
DMA modes (PXI/PCI only)...............................
16,384 samples
8,192 samples
DMA, interrupts, programmed I/O
Scatter-gather
FIFO buffer size................................................. 2,048 samples
Data transfers .................................................. DMA, interrupts, programmed I/O
DMA modes ..................................................... Scatter gather
Voltage Output
Ranges.............................................................. ±10 V
Output coupling ................................................ DC
Protection ......................................................... Short-circuit to ground
Voltage Output
Ranges.............................................................. ±10.0 V, ±AO EXT REF
Output coupling ................................................ DC
Protection ......................................................... Short-circuit to ground
Digital I/O
Number of channels.........................................
Compatibility ....................................................
Power-on state .................................................
Data transfers ..................................................
8 input/output
TTL/CMOS
Input (high-impedance)
Programmed I/O
Digital I/O
Number of channels.........................................
Compatibility ....................................................
Power-on state .................................................
Data transfers ..................................................
Input buffer.......................................................
Output buffer ....................................................
Transfer rate .....................................................
8 input/output
5 V TTL/CMOS
Input (high-impedance)
Programmed I/O, DMA (NI 673x), interrupts (NI 673x)
2048 bytes (NI 673x)
2048 bytes (NI 673x)
10 Mwords/s (NI 673x)
Timing I/O
Number of channels
Up/down counter/timers ...........................
Frequency scaler........................................
Resolution
Up/down counter/timers ...........................
Frequency scaler........................................
Compatibility ....................................................
Digital logic levels
Level
Input low voltage
Input high voltage
Output low voltage (I
out
= 5 mA)
Output high voltage (I
out
= -3.5 mA)
2
1
24 bits
4 bits
5 V TTL/CMOS
Min
0.0 V
2.0 V
4.35 V
Max
0.8 V
5.0 V
0.4 V
Timing I/O
General-Purpose Up/Down Counter/Timers
Number of channels......................................... 2
Resolution......................................................... 24 bits
Compatibility .................................................... 5 V TTL/CMOS
Digital logic levels
Level
Input low voltage
Input high voltage
Output low voltage (I
out
= 5 mA)
Output high voltage (I
out
= -3.5 mA)
Minimum
0V
2V
4.35 V
Maximum
0.8 V
5V
0.4 V
Data transfers
Up/down counter/timers ........................... DMA (scatter-gather), interrupts, programmed I/O
Frequency scaler........................................ Programmed I/O
Base clocks available....................................... 20 MHz and 100 kHz
Data transfers .................................................. DMA (except NI 6715), interrupts, programmed I/O
DMA modes (PCI/PXI only)............................... Scatter-gather
Digital Trigger
Purpose
Analog Output ...........................................
Counter/timers...........................................
Source...............................................................
Compatibility ....................................................
Response ..........................................................
Start trigger, gate, clock
Source, gate
PFI <0..9>
5 V TTL
Rising or falling edge
Digital Trigger
Purpose
Analog output ............................................
General-purpose counter/timers ...............
Source...............................................................
Slope.................................................................
Compatibility ....................................................
Start trigger, gate, clock
Source, gate
PFI <0...9>, RTSI <0...6> (except NI 6715)
Positive or negative; software selectable
5 V TTL/CMOS
For more detailed specifications, please refer to the product manual.
National Instruments • Tel: (800) 813 3693 • info@ni.com • ni.com
5