74HC574-Q100; 74HCT574-Q100
Nexperia
Octal D-type flip-flop; positive edge-trigger; 3-state
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
3-state output enable input (active LOW)
data input
D[0:7]
GND
CP
2, 3, 4, 5, 6, 7, 8, 9
10
11
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
Q[0:7]
VCC
19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
20
supply voltage
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
OE
L
Internal
flip-flop
Output
CP
Dn
Qn
L
Load and read register
Load register and disable output
l
L
L
h
l
H
L
H
Z
H
H
h
H
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
35
+70
70
+150
500
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
65
[1]
-
mW
[1] For SO20 packages: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
74HC_HCT574_Q100
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Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 26 January 2015
4 of 17
NEXPERIA [ Nexperia ]
