11.Instruction description
11.1Outline
To overcome the speed difference between the internal clock of KS0066U and the MPU clock, KS0066U
performs internal operations by storing control in formations to IR or DR. The internal operation is determined
according to the signal from MPU, composed of read/write and data bus (Refer to Table7).
Instructions can be divided largely into four groups:
1) KS0066U function set instructions (set display methods, set data length, etc.)
2) Address set instructions to internal RAM
3) Data transfer instructions with internal RAM
4) Others
The address of the internal RAM is automatically increased or decreased by 1.
Note: during internal operation, busy flag (DB7) is read “High”.
Busy flag check must be preceded by the next instruction.
11.2 Instruction Table
Instruction code
DB
Execution
time (fosc=
270 KHZ
Instruction
Description
DB
1
RS R/W DB7 DB6
DB4 DB3 DB2
DB0
5
Write “20H” to DDRA and set
DDRAM address to “00H” from
AC
Set DDRAM address to “00H”
From AC and return cursor to
Its original position if shifted.
The contents of DDRAM are
not changed.
Clear
1.53ms
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Display
Return
Home
1.53ms
39us
0
1
-
Assign cursor moving direction
And blinking of entire display
Entry mode
Set
Display ON/
OFF control
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
I/D SH
Set display (D), cursor (C), and
Blinking of cursor (B) on/off
Control bit.
Set cursor moving and display
Shift control bit, and the
Direction, without changing of
DDRAM data.
Set interface data length (DL:
8-
D
C
-
B
-
Cursor or
39us
39us
0
0
0
0
0
0
0
0
1
1
S/C R/L
Display shift
Function
set
Bit/4-bit), numbers of display
Line (N: =2-line/1-line) and,
Display font type (F: 5x11/5x8)
Set CGRAM address in
address
0
1
DL
N
F
-
-
Set
39us
39us
CGRAM
Address
Set
0
0
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
Counter.
Set DDRAM address in
address
Counter.
DDRAM
Address
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Whether during internal
Operation or not can be known
By reading BF. The contents of
Address counter can also be
read.
Read busy
Flag and
Address
0us
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write data into internal RAM
(DDRAM/CGRAM).
Write data
to
Address
Read data
From RAM
43us
43us
1
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Read data from internal RAM
(DDRAM/CGRAM).
NOTE:
When an MPU program with checking the busy flag (DB7) is made, it must be necessary 1/2fosc is
necessary for executing the next instruction by the falling edge of the “E” signal after the busy flag (DB7) goes
to “Low”.
9
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