MPU Interface
When DL is set for 8‐bit mode, the display interfaces with the MPU with DB7..DB0 (DB7 is the MSB).
When DL is set for 4‐bit mode, the display interfaces with the MPU with only DB7..DB4 (DB7 is the MSB). Each
instruction must be sent in two operations, the 4 high‐order bits first, followed by the 4 low‐order bits. The Busy Flag
must be checked after completion of the entire 8‐bit instruction.
6800‐MPU Parallel Interface (default)
RS
tAS68
tAH68
CSB
tCY68
tPW68(W)
tPW68(R)
0.9VDD
0.1VDD
E
tDH68
tDS68
DB0 to DB7
DB0 to DB7
tOD68
tACC68
Item
Signal
RS
RS
Symbol
tAS68
tAH68
Min.
20
0
500
250
250
40
20
‐
10
Typ. Max. Unit
Note
Address setup time
Address hold time
System cycle time
Pulse width (write)
Pulse width (read)
Data setup time
Data hold time
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCY68
E
E
tPW68(W)
tPW68(R)
tDS68
tDH68
tACC68
tOD68
DB7..DB0
DB7..DB0
DB7..DB0
DB7..DB0
‐
180
‐
Read access time
Output disable time
CL=100pF
[11]
NEWHAVEN [ NEWHAVEN DISPLAY INTERNATIONAL, INC. ]
