RoHS
RoHS
4PT Series
SEMICONDUCTOR
Fig.4 Relative variation of thermal impedance
junction to ambient versus pulse duration
(DPAK)
Fig.3 Average and DC on-state current versus
ambient temperature (DPAK)
K=[Zth(j-c)/Rth(j-c)]
IT(AV)(A)
1E+0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
Device mounted on FR4 with
recommended pad layout
Z
th(j-c)
DPAK (S = 0.5cm²)
DC
α=180°
1E-1
Z
th(j-a)
IPAK
DC
1E-2
1E-3
α=180°
Device mounted on FR4 with
recommended pad layout
0.2
0.0
t
(s)
T
(°C)
p
amb
0
25
50
75
100
125
1E-3
1E-2
1E-1
1E+0
1E+1
5E+2
1E+2
Fig.5 Relative variation of gate trigger current
and holding current versus junction
temperature
Fig.6 Relative variation of holding current
versus gate-cathode resistance
(typical values)
IH[RGK] / IH[RGK=1KΩ
IGT,IH,IL[Tj] / IGT,IH,IL[Tj=25 C]
5
2.0
Tj=25°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
4
3
2
IGT
lhand IL
RGK=1KΩ
0.4
T (°C)
j
1
0
0.2
0.0
RGK(KΩ)
-40 -20
0
20
40
60
80
100 120 140
1E-2
1E-1
1E+0
1E+1
Fig.8 Relative variation of dV/dt immunity
versus gate-cathode capacitance
(typical values)
Fig.7 Relative variation of dV/dt immunity
versus gate-cathode resistance
(typical values)
dV/dt[RGK] / dV/dt[RGK=220Ω]
dV/dt[CGK] / dV/dt[RGK=220Ω]
10.00
1.00
10
Tj=125 C
VD=0.67 X VDRM
VD=0.67 X VDRM
Tj=125°C
8
6
4
2
0
R
=220Ω
GK
0.10
0.01
C
(nF)
R
(KΩ)
GK
GK
0
200
600 800 1000 1200 1400
1800 2000
6
400
1600
0
2
8
10 12 14 16 18
22
4
20
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