Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal Bus
4
2
2
2
(IME)
IPS
IST
IM1
IM0
Interrupt Enable Flag (IE XXX
)
Decoder
INT
BT
IRQBT
IRQ4
Both Edges
Detection
Circuit
INT4
/P00
VRQn
Edge
INT0
/P10
Detection
Circuit
IRQ0
*
Edge
INT1
/P11
Vector
Table
Address
Generator
Circuit
IRQ1
Detection
Circuit
*
Priority Control
Circuit
INTSIO
IRQSIO
IRQT0
IRQTPG
IRQKS
IRQW
IRQ2
INTT0
INTTPG
INTKS
INTW
Standby Release
Signal
Rising Edge
Detection
Circuit
INT2
/P12
µ
*
Noise eliminator