CHAPTER 4 PORT FUNCTIONS
(3) Block diagram (port 5)
Figure 4-12. Block Diagram of P50, P51, and P53
EVDD
WRPU
PU5
P-ch
PU5n
WRPFC
WRPMC
WRPM
PFC5
PFC5n
PMC5
PMC5n
PM5
PM5n
WRPORT
RTP0n output
Output latch
(P5n)
P50/TI011/RTP00/KR0,
P51/TI50/RTP01/KR1,
P53/SIA0/RTP03/KR3
RD
Address
TI011, TI50, SIA0 input
KRn input
Remarks 1. PU5: Pull-up resistor option register 5
PFC5: Port 5 function control register
PM5: Port 5 mode register
PMC5: Port 5 mode control register
RD:
Port 5 read signal
WR: Port 5 write signal
2. n = 0, 1, 3
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User’s Manual U15862EJ3V0UD